PDF《with Integrated Transceiver》

21 8.3 Feature Description.24 8.4 Device Functional Modes.27 8.5 Programming

41 8.6 Register Maps.44

9 Application and Implementation

127 9.1 Application Design Consideration

127 9.2 Typical Application

131 10 Power Supply Recommendations

134 11 Layout.135 11.1 Layout Guidelines

135 11.2 Layout Example

136 12 Device and Documentation Support

137 12.1 Documentation Support

137 12.2 Receiving Notification of Documentation Updates.137 12.3 Community Resources.137 12.4 Trademarks.137 12.5 Electrostatic Discharge Caution.137 12.6 Glossary.138

13 Mechanical, Packaging, and Orderable Information

138 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2017) to Revision A Page ? Changed the document status From: Advanced Information To: Production data

1 3 TCAN4550-Q1 www.ti.com SLLSEZ5A CJANUARY 2018CREVISED APRIL

2019 Product Folder Links: TCAN4550-Q1 Submit Documentation Feedback Copyright ? 2018C2019, Texas Instruments Incorporated (1) Note: DI = Digital Input;

DO = Digital Output;

HV = High Voltage;

Thermal PAD and GND Pins must be soldered to GND

5 Pin Configuration and Functions RGY Package

20 Pin (VQFN) Top View Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 OSC1 I External crystal oscillator or clock input

2 nWKRQ DO Wake request (active low)

3 GPIO1 DI/O Configurable input/output function pin through SPI

4 SCLK DI SPI clock input

5 SDI DI SPI slave data input from master output

6 SDO DO SPI slave data output to master input

7 nCS DI SPI chip select

8 nINT DO Interrupt pin to MCU (active low)

9 GPO2 DO Configurable output function pin through SPI

10 CANL HV Bus I/O Low level CAN bus line

11 CANH HV Bus I/O High level CAN bus line

12 WAKE HVI Wake input, high voltage input

13 GND GND Ground connection

14 VSUP HV Supply In Supply from battery

15 INH HVO Inhibit to control system voltage regulators and supplies (open drain)

16 VCCOUT Supply Out

5 V regulated output

17 VIO Supply In Digital I/O voltage supply

18 FLTR ― Internal regulator filter, requires external capacitor to ground

19 RST DI Device reset

20 OSC2 O External crystal oscillator output;

when using single input clock to OSC1 this pin should be connected to ground

4 TCAN4550-Q1 SLLSEZ5A CJANUARY 2018CREVISED APRIL

2019 www.ti.com Product Folder Links: TCAN4550-Q1 Submit Documentation Feedback Copyright ? 2018C2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range for C

40 ℃ ≤ TA ≤

125 ℃ (unless otherwise noted)(1) MIN MAX UNIT VSUP Supply voltage C0.3

42 V VIO Supply voltage I/O level shifter C0.3

6 V VCCOUT

5 V output supply C0.3

6 V VBUS CAN bus I/O voltage (CANH, CANL) C58

58 V VWAKE WAKE pin input voltage C0.3

42 V VINH Inhibit pin output voltage C0.3

42 V VLogic_Input Logic input terminal voltage C0.3

6 V VSO Digital output terminal voltage C0.5

6 V IO(SO) Digital output current

8 mA IO(INH) Inhibit output current

4 mA IO(WAKE) Wake current if due to ground shift V(WAKE) ≤ V(GND) C 0.3 V