PDF《现代计算机组成原理》

现代计算机组成原理 潘明潘松编著 科学出版社 科学出版社 第6章16位CISC CPU设计 6.

1 顶层系统设计 6.1.1 16位CPU的组成结构 图6-1 16位CPU结构框图 6.1 顶层系统设计 6.1.2指令系统设计 (1)单字指令 1.指令格式 表6-1 单字节指令格式 6.1 顶层系统设计 (2)双字指令 表6-2 双字指令格式 表6-3 双字节指令 6.1 顶层系统设计 6.1.2指令系统设计 2.指令操作码 表6-4 操作码功能表 6.1 顶层系统设计 6.1.2指令系统设计 2.指令操作码 表6-5 常用指令举例 6.1 顶层系统设计 6.1.3 顶层结构的VHDL设计 1. CPU元件的VHDL描述 【例6-1】CPU_LIB.VHD library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

package cpu_lib is type t_shift is (shftpass, shl, shr, rotl, rotr);

subtype t_alu is unsigned(3 downto 0);

(接下页) 6.1 顶层系统设计 6.1.3 顶层结构的VHDL设计 1. CPU元件的VHDL描述 constant alupass : unsigned(3 downto 0) := "0000";

constant andOp : unsigned(3 downto 0) := "0001";

constant orOp : unsigned(3 downto 0) := "0010";

constant notOp : unsigned(3 downto 0) := "0011";

constant xorOp : unsigned(3 downto 0) := "0100";

constant plus : unsigned(3 downto 0) := "0101";

constant alusub : unsigned(3 downto 0) := "0110";

constant inc : unsigned(3 downto 0) := "0111";

constant dec : unsigned(3 downto 0) := "1000";

constant zero : unsigned(3 downto 0) := "1001";

type t_comp is (eq, neq, gt, gte, lt, lte);

subtype t_reg is std_logic_vector(2 downto 0);

type state is (reset1, reset2, reset3, reset4, reset5,reset6, execute, nop, load, store, move, load2, load3, load4, store2, store3,store4, move2, move3, move4,incPc, incPc2, incPc3, incPc4, incPc5, incPc6, loadPc,loadPc2,loadPc3, loadPc4, bgtI2, bgtI3, bgtI4, bgtI5, bgtI6, bgtI7,bgtI8, bgtI9,bgtI10, braI2, braI3, braI4, braI5, braI6, loadI2,loadI3, loadI4, loadI5, loadI6,inc2, inc3, inc4);

subtype bit16 is std_logic_vector(15 downto 0);

end cpu_lib;

6.1 顶层系统设计 6.1.3 顶层结构的VHDL设计 1. CPU元件的VHDL描述 【例6-2】top.vhd library IEEE;

use IEEE.std_logic_1164.all;

use work.cpu_lib.all;

entity top is end top;

architecture behave of top is component mem port (addr : in bit16;

sel,rw : in std_logic;

ready : out std_logic;

data : inout bit16);

end component;

component cpu port(clock, reset, ready : in std_logic;

addr : out bit16;

rw, vma : out std_logic;

data : inout bit16);

end component;

signal addr, data : bit16 ;

signal vma, rw, ready : std_logic;

signal clock, reset : std_logic := '0';

begin clock