PDF《HMC704LP4E》

HMC704LP4E v04.

0215

8 GHZ FRACTIONAL-N PLL PLLs - SMT

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1 Typical Applications The HMC704LP4E is ideal for: ? Microwave Point-to-Point Radios ? Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) ? Wireless LANs, WiMAX ? Communications Test Equipment ? CATV Equipment ? Automotive Functional Diagram Features Wide band: DC -

8 GHz RF Input,

4 GHz 19-bit Prescaler Industry Leading Phase Noise &

Spurious: -112 dBc/Hz @

8 GHz Fractional,

50 kHz Offset Figure of Merit -230 dBc/Hz Fractional Mode -233 dBc/Hz Integer Mode

100 MHz PFD High PFD rate:

100 MHz

24 Lead 4x4 mm SMT Package:

16 mm2 General Description The HMC704LP4E has been designed for the best phase noise and lowest spurious content possible in an integrated PLL. Fabricated in a SiGe BiCMOS process, this Fractional-N PLL con? sists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump. Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster fre?quency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional mod? ulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems. The serial interface offers read back capability and is compatible with a wide variety of protocols.

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8 GHZ FRACTIONAL-N PLL Table 1. Electrical Specifications VDDCP, VPPCP = 5V+/-4%;

RVDD, AVDD, DVDD, VDDPD, VCCPS = 3.3V +/-10%;

AGND = DGND = 0V Parameter Conditions Min. Typ. Max. Units RF INPUT CHARACTERISTICS [6][7] RF Input Frequency Range [1] DC

8000 MHz Prescaler Input Freq Range [1] DC

4000 MHz Power Range [13] -15 -7 -3 dBm Impedance

100 Ohms each leg||3pF 100||3 Ohms||pF REF INPUT CHARACTERISTICS Frequency Range (3.3V) [1][8] DC

50 350 MHz Power from 50Ohm Source [12]

6 dBm Impedance 100||3 Ohms||pF Ref Divider Range (14 bit)

1 16,383 PHASE DETECTOR RATE [1][12] Integer Mode DC

50 115 MHz Fractional Mode A DC

50 80 MHz Fractional Mode B DC

50 100 MHz CHARGE PUMP Output Current 20uA Steps 0.02 2.5 mA POWER SUPPLIES RVDD, AVDD, VCCPS, VCCHF, VCCPD - Analog supply All should be equal 3.0 3.3 3.5 V DVDD - Digital supply 3.0 3.3 3.5 V VDDLS, VPPCP Charge Pump VDDLS, VPPCP must be equal 3.0 5.0 5.2 V 3.3V - Current consumption [9]

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58 mA 5V - Current consumption All Modes

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7 mA Power Down Current [10]

100 uA BIAS Reference Voltage Pin 12. Measured with 10GOhm Meter 1.880 1.920 1.960 V PHASE NOISE Flicker Figure of Merit (FOM)[2] -266 dBc/Hz Floor Figure of Merit [11] Integer HiK Mode Integer Normal Mode Fractional HiK Mode [3] Fractional Normal Mode [3] -236 -232 -232 -228 -233 -230 -230 -227 -231 -228 -227 -225 dBc/Hz dBc/Hz dBc/Hz dBc/Hz Flicker Noise at foffset PNflick = Flicker FOM +20log(fvco) -10log(foffset) dBc/Hz Phase Noise Floor at fvco with fpd PNfloor = Floor FOM + 10log(fpd) +20log(fvco/fpd) dBc/Hz Total Phase Noise vs foffset, fvco, fpd PN = 10log(10(PNflick /10) + 10(PNfloor /10) ) dBc/Hz Jitter SSB 100Hz to 50kHz

50 fs SPURIOUS [4][5] Integer Boundary Spurs @~8GHz offsets less than loop band- width, fpd = 50MHz -60 -52 dBc PLLs - SMT

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8 GHZ FRACTIONAL-N PLL Parameter Conditions Min. Typ. Max. Units LOGIC INPUTS Switching Threshold (Vsw) VIH/VIL within 50mV of Vsw

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54 % DVDD LOGIC OUTPUTS VOH Output High Voltage VDD-0.4 V VOL Output Low Voltage 0.4 V Digital Output Driver Delay SCK to Digital Output Delay 0.5ns+0.2ns/pF 8.2ns+0.2ns/pF ns ns RF divider 8GHz Integer Mode