PDF《SN74AHC245-EP OCTAL BUS TRANSCEIVER》

SN74AHC245-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCLS487A C MAY

2003 C REVISED JUNE

2003 1 POST OFFICE BOX

655303 ? DALLAS, TEXAS

75265 D Controlled Baseline C One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of C55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree? D Operating Range 2-V to 5.

5-V VCC D Latch-Up Performance Exceeds

250 mA Per JESD

17 D ESD Protection Exceeds

1000 V Per MIL-STD-833, Method 3015;

Exceeds

100 V Using Machine Model (C =

200 pF, R = 0) ? Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. description/ordering information The SN74AHC245 octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE? ORDERABLE PART NUMBER TOP-SIDE MARKING 55°C to 125°C SOIC C DW Tape and reel SN74AHC245MDWREP AHC245MEP C55°C to 125°C TSSOP C PW Tape and reel SN74AHC245MPWREP AHC245EP ? Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright ? 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DW OR PW PACKAGE (TOP VIEW)

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12 11 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND VCC OE B1 B2 B3 B4 B5 B6 B7 B8 SN74AHC245-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCLS487A C MAY

2003 C REVISED JUNE

2003 2 POST OFFICE BOX

655303 ? DALLAS, TEXAS

75265 FUNCTION TABLE (each transceiver) INPUTS OPERATION OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation logic symbol? ? This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. B2

17 B3

16 B4

15 A5

6 A6

7 A7

8 A8

9 A2

3 A3

4 A4

5 OE A1

2 G3

19 3 EN2 [AB] B5

14 B6

13 B7

12 B8

11 B1

18 3 EN1 [BA]

1 DIR

1 2 logic diagram (positive logic) DIR OE A1 B1 To Seven Other Channels

1 2

19 18 SN74AHC245-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCLS487A C MAY

2003 C REVISED JUNE

2003 3 POST OFFICE BOX