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1 input. PA2/T0CK/INT/COUT /AN2 I/O Port A, Schmitt Trigger input level, with program pull_hi and interrupt on pin change. Timer0 clock input. External interrupt. Comparator output. A/D Channel

2 input. PA3/MCLR I Port A, TTL input level, with program interrupt on pin change. Master clear. Schmitt Trigger input level. PA4/OSC2/T1G/AN3 I/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Oscillator crystal output, in RC mode clock output Fosc/4 frequency. Timer1 gate. A/D Channel

3 input. PA5/OSC1/T1CKI I/O Port A, TTL input level, with program pull_hi and interrupt on pin change. Oscillator crystal input/external clock source input. Timer1 clock input. PC0/AN4 I/O Port C, TTL input level. A/D Channel

4 input. PC1/AN5 I/O Port C, TTL input level. A/D Channel

5 input. PC2/AN6 I/O Port C, TTL input level. A/D Channel

6 input. PC3/AN7 I/O Port C, TTL input level. A/D Channel

7 input. PC4~5 I/O Port C, TTL input level. Vdd Power supply Vss Ground http://www.mx mcu.com.cn MDT10F676 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 4/18 2010.6 Ver. 1.1 8. Memory Map 8.1 Program memory : 0000H Reset Vector 0001H 0002H 0003H 0004H Peripheral interrupt Vector 0005H Program memory 03FFH http://www.mx mcu.com.cn MDT10F676 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 5/18 2010.6 Ver. 1.1 8.2 Register file map : Address Description Address BANK

0 BANK

1 00 IAR IAR

80 01 RTCC TMR

81 02 PCL PCL

82 03 STATUS STATUS

83 04 MSR MSR

84 05 PORT A CPIO A

85 06

86 07 PORT C CPIO C

87 08~09 88~89 0A PCHLAT PCHLAT 8A 0B INTS INTS 8B 0C PIFB1 PIEB1 8C 0D 8D 0E TMR1L PSTA 8E 0F TMR1H 8F

10 T1STA INOSCR

90 11 ADINS

91 12~14 92~94

15 PAPHR

95 16 PAINTR

96 17~18 97~98

19 CMSTA VRSTA

99 1A EEDATA 9A 1B EEADR 9B 1C EECON1 9C 1D EECON2 9D 1E ADRESH ADRESL 9E 1F ADS0 ADS1 9F

64 Mapped 20~5F Genreal in A0~DF Register Bank0 60~7F E0~FF Unimplemented memory location. http://www.mx mcu.com.cn MDT10F676 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 6/18 2010.6 Ver. 1.1 (1). 00H or 80H : IAR ( Indirect Address Register) Use contents of MSR to address data memory (not a physical register) (2). 01H : RTCC (Timer0 Counter). 8-bit real time clock/counter (3). 02H or 82H : PCL (Program Counter Low Byte) Low order

8 bits of the Program Counter (PC) (4). 03H or 83H : STATUS (Status register). Bit Symbol Function

0 1

2 3

4 5 6―7 C HC Z /PF /TF page ―― Carry bit Half Carry bit Zero bit Power loss Flag bit WDT time-out Flag bit Register page select bit :

0 : 00H --- 7FH

1 : 80H --- FFH General purpose bit (5). 04H or 84H : MSR (Memory Select Register) Memory Bank Select Register :

0 : 00~7F (Bank0)

1 : 80~FF (Bank1) MSR Bit

7 Bit

6 Bit

5 Bit

4 Bit

3 Bit

2 Bit

1 Bit

0 Indirect Addressing Mode (6). 05H : Port A data output register. Bit

7 Bit

6 Bit

5 Bit

4 Bit

3 Bit

2 Bit

1 Bit

0 Port A - - PA5 PA4 PA3 PA2 PA1 PA0 Bit 7-6 : Unimplemented Bit 5-0 : PA5~PA0, I/O Register (7). 06H : Unimplemented Register. http://www.mx mcu.com.cn MDT10F676 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 7/18 2010.6 Ver. 1.1 (8). 07H : Port C data output register Bit