PDF《XRD8785》

245 350

550 ? Ladder Temp. Coefficient RTCO

2000 ppm/°C Self Bias

1 Short VRB and VRBS VRB 0.6 V Short VRT and VRTS VRT-VRB

2 V Self Bias

2 VRB = AGND, VRT 2.3 V Short VRT and VRTS ANALOGINPUT Input Bandwidth (C1 dB)2,

4 BW

50 MHz Input Voltage Range VIN VRB VRT V Input Capacitance

5 CIN

16 pF Aperture Delay2 tAP

3 ns DIGITALINPUTS Logical "1" Voltage VIH 4.0 V Logical "0" Voltage VIL 1.0 V DC Leakage Currents

6 IIN VIN =DGND to DVDD CLK

5 ?A OE

5 ?A Input Capacitance

5 pF Clock Timing ( See Figure 1.)7 Clock Period 1/FS

50 66.7 ns High Pulse Width tPWH

25 33.3 ns Low Pulse Width tPWL

25 33.3 ns DIGITALOUTPUTS COUT =15 pF Logical "1" Voltage VOH 4.5 V I LOAD =

4 mA Logical "0" Voltage VOL 0.4 V I LOAD =

4 mA 3-state Leakage IOZ

10 ?A V OUT =DGND to DVDD Data Valid Delay

8 tDL

10 ns Data Enable Delay tDEN

5 ns Data 3-state Delay tDHZ

5 ns XRD8785

4 Rev. 3.00 ELECTRICALCHARACTERISTICSTABLE(CONT'D) UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 5V, FS = 15MHZ (50% DUTY CYCLE), VRT = 2.6V, VRB = 0.6V, TA = 25°C 25°C Parameter Symbol Min Typ Max Units TestConditions/Comments ACPARAMETERS Differential Gain Error dg

2 % FS =

4 x NTSC Differential Phase Error dph

1 Degree FS =

4 x NTSC POWERSUPPLIES Operating Voltage (AVDD, DVDD)9 VDD 4.5

5 5.5 V Current (AGND + DGND) IDD

15 25 mA Does not include ref. current NOTES 1. The difference between the measured and theideal code width (VREF/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4). Accuracy is a function of the sampling rate (FS). 2.Guaranteed,nottested 3. Specified values guarantee functionality. Refer to other parameters for accuracy. 4. C1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5. See VIN input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance. 6. All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7. tR , tF should be limited to >5ns for best results. 8.DependsontheRCloadconnectedtotheoutputpin. 9. AGND&DGNDpinsareconnectedthroughthesiliconsubstrate.Connecttogetheratthepackageandtotheanaloggroundplane. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2,

3 VDD to GND 7V VRT & V RB.VDD +0.5 to GND C0.5V VIN VDD +0.5 to GND C0.5V All Inputs VDD +0.5 to GND C0.5V All Outputs VDD +0.5 to GND C0.5V StorageTemperature

65 to +150°C LeadTemperature(Soldering10seconds) ...+300°C Package Power Dissipation Rating @ 75°C PDIP, SOIC, SOP 675mW Deratesabove75°C 12mW/°C NOTES: 1.Stressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperationatorabovethisspecification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2.AnyinputpinwhichcanseeavalueoutsidetheabsolutemaximumratingsshouldbeprotectedbySchottkydiodeclamps(HP5082-2835)frominputpintothesupplies.Allinputshaveprotection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3. VDD refers to AVDD and DVDD. GND refers to AGND and DGND. XRD8785

5 Rev. 3.00 Figure 1. XRD8785 Timing Diagram Figure 2. Output Enable/Disable Timing Diagram Figure 3. DNL Measurement Figure 4. INL Error Calculation XRD8785