编辑: 捷安特680 2019-07-14

3 Fig 4. Normalized On-Resistance Vs. Temperature Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics -60 -40 -20

0 20

40 60

80 100

120 140

160 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 T , Junction Temperature ( C) R , Drain-to-Source On Resistance (Normalized) J DS(on) ° V = I = GS D 10V 44A 0.1

1 10

100 VDS, Drain-to-Source Voltage (V) 0.1

1 10

100 1000 I D , Drain-to-Source Current (A) 5.0V 300?s PULSE WIDTH Tj = 25°C VGS TOP 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 0.1

1 10

100 VDS, Drain-to-Source Voltage (V) 0.1

1 10

100 I D , Drain-to-Source Current (A) 5.0V 300?s PULSE WIDTH Tj = 175°C VGS TOP 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0 7.0 9.0 11.0 13.0 15.0 VGS, Gate-to-Source Voltage (V) 1.00 10.00 100.00 1000.00 I D , Drain-to-Source Current (Α ) TJ = 25°C TJ = 175°C VDS = 15V 300?s PULSE WIDTH IRFB/IRFS/IRFSL38N20D

4 www.irf.com Fig 8. Maximum Safe Operating Area Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode Forward Voltage

1 10

100 1000 VDS, Drain-to-Source Voltage (V)

10 100

1000 10000

100000 C, Capacitance(pF) Coss Crss Ciss VGS = 0V, f =

1 MHZ Ciss = C gs + C gd, C ds SHORTED Crss = C gd Coss = C ds+ C gd

0 10

20 30

40 50

60 70 QG Total Gate Charge (nC)

0 2

4 6

8 10

12 V GS , Gate-to-Source Voltage (V) VDS= 160V VDS= 100V ID= 26A 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-toDrain Voltage (V) 0.10 1.00 10.00 100.00 1000.00 I SD , Reverse Drain Current (A) TJ = 25°C TJ = 175°C VGS = 0V

1 10

100 1000 VDS , Drain-toSource Voltage (V) 0.1

1 10

100 1000 I D , Drain-to-Source Current (A) Tc = 25°C Tj = 175°C Single Pulse 1msec 10msec OPERATION IN THIS AREA LIMITED BY RDS(on) 100?sec IRFB/IRFS/IRFSL38N20D www.irf.com

5 Fig 10a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr td(off) tf Fig 10b. Switching Time Waveforms VDS Pulse Width ≤

1 ?s Duty Factor ≤ 0.1 % RD VGS RG D.U.T. 10V + -VDD Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig 9. Maximum Drain Current Vs. Case Temperature

25 50

75 100

125 150

175 0

10 20

30 40

50 T , Case Temperature ( C) I , Drain Current (A) ° C D 0.001 0.01 0.1

1 0.00001 0.0001 0.001 0.01 0.1

1 Notes: 1. Duty factor D = t / t 2. Peak T = P x Z + T

1 2 J DM thJC C P t t DM

1 2 t , Rectangular Pulse Duration (sec) Thermal Response (Z )

1 thJC 0.01 0.02 0.05 0.10 0.20 D = 0.50 SINGLE PULSE (THERMAL RESPONSE) IRFB/IRFS/IRFSL38N20D

6 www.irf.com QG QGS QGD VG Charge D.U.T. VDS ID IG 3mA VGS .3?F 50K? .2?F 12V Current Regulator Same Type as D.U.T. Current Sampling Resistors + -

10 V Fig 13b. Gate Charge Test Circuit Fig 13a. Basic Gate Charge Waveform Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Fig 12a. Unclamped Inductive Test Circuit tp V(BR)DSS IAS R G IAS 0.01? tp D.U.T L VDS + - VD D DRIVER A 15V 20V

25 50

75 100

125 150

175 0

180 360

540 720

900 Starting Tj, Junction Temperature ( C) E , Single Pulse Avalanche Energy (mJ) AS ° ID TOP BOTTOM 11A 19A 26A IRFB/IRFS/IRFSL38N20D www.irf.com

7 P.W. Period di/dt Diode Recovery dv/dt Ripple ≤ 5% Body Diode Forward Drop Re-Applied Voltage Reverse Recovery Current Body Diode Forward Current VGS=10V VDD ISD Driver Gate Drive D.U.T. ISD Waveform D.U.T. VDS Waveform Inductor Curent D = P.W. Period + - + + + - - - Fig 14. For N-Channel HEXFET? Power MOSFETs * VGS = 5V for Logic Level Devices Peak Diode Recovery dv/dt Test Circuit ? ? ? RG VDD ? dv/dt controlled by RG ? Driver same type as D.U.T. ? ISD controlled by Duty Factor D ? D.U.T. - Device Under Test D.U.T Circuit Layout Considerations ? Low Stray Inductance ? Ground Plane ? Low Leakage Inductance Current Transformer ? * IRFB/IRFS/IRFSL38N20D

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