PDF《CREATING A BIPOLAR INPUT RANGE FOR》

100 268 C83.4 249,762

350 2000

50 186 C165.4 495,428 TABLE 1. Various Configurations and the Associated Full Scale Ranges and Zero Input Signal DDC112 Output Codes. + Full Scale FFFFFh = 1,048,575 INPUT SIGNAL DDC112 OUTPUT CODE Zero 01000h =

4096 C Full Scale 00000h SBAA034

2 For example, consider a DDC112 configured with a Range and TINT equal to 250pC and 500?s respectively. A 20M? offset resistor connected to 4.1V results in a positive full scale of 147.5pC, a negative full-scale of C103.5pC. When the input signal is zero, the DDC112 output code reads 90,079. Figure

3 shows the DDC112'

s output code versus signal level for this example. In general, the output code with a zero input signal is where QFS is the selected Range. Remember, however, that during the A/D conversions, VREF is sampled by the DDC112, which tends to produce glitches on this node. For a single DDC112 system, using Figure 4'

s op amp buffer and large bypass capacitors reduces the glitches sufficiently so that VREF can also directly drive the resistor. But, for multiple DDC112 systems, the glitches will be larger and may interfere with generating the offset currents. In that case, use a separate buffer to drive the resistors as shown in Figure 5. If VREF (typically 4.1V) is too large of a voltage, use a resistor voltage divider as shown in Figure 6. Keep the sum of the resistor values large enough as not to load the op amp;

(R1 + R2) >

100k? should be fine. Additionally, use a capacitor in parallel with R2 to help lowpass filter the noise on that node. And finally, it is a good idea to place the resistor as close to the DDC112'

s input as possible and to surround it with ground shielding. The input is very susceptible to pickup. Keeping it short and shielded can dramatically reduce cou- pling from 60Hz and other sources. There are a few things to mention about the circuit in Figure 2. First, use a large resistor, preferably greater than 10M?. A large resistor better approximates an ideal current source and actually helps reduce the thermal noise seen at the DDC112'

s output (discussed in more detail in the last section). The voltage coefficient of the resistor doesn'

t matter, but the temperature coefficient may, if the offset drift over tempera- ture is a concern. In most cases, Caddock'

s MK632 series of high valued resistors are a good choice. Second, a convenient voltage for the resistor is the VREF signal used by the DDC112, see Figure 4. FIGURE 3. DDC112 Output Code vs Input Signal with Offset Applied. FIGURE 5. Typical Circuit Implementation to Add Offset When Using Multiple DDC112s. R Current from Sensor 10?F 10?F To other DDC112s 0.1?F OPA2350 VREF IN DDC112 To other Resistors VREF OPA2350 VREF R Current from Sensor 10?F 0.1?F OPA350 VREF IN DDC112 FIGURE 4. Typical Circuit Implementation to Add Offset. FIGURE 6. Resistor Divider to Reduce Voltage Applied to Offset Resistor. 1?F OPA350 IN R R1 R2 DDC112 Current from Sensor VREF 10?F Output Code V R T Q ZEROINPUT INT FS = + ( ) ? ? ? ?

4096 2

1 20 C (1) +Full Scale = 147.5pC FFFFFh = 1,048,575 INPUT SIGNAL DDC112 OUTPUT CODE Zero 69F5Ch = 434,012 TINT = 500?s Range = 250pC R = 20M? V = 4.1V CFull Scale = C103.5pC 00000h

3 Insert Resistors to Generate Offset Set Jumpers A and B Coaxial Cable FIGURE 7. Using the Evaluation Fixture to Create a Bipolar Input Range. FIGURE 8. DDC112 Output Code and Evaluation Fixture Software Reading vs Input Signal with Offset Applied. EVALUATION FIXTURE The DDC112 Evaluation Fixture quickly configures to in- corporate the circuit in Figure 4. Simply set jumpers J1A and J1B and connect VREF to the resistor using a short coaxial cable on the DUT board as illustrated in Figure 7. After- wards, apply the input signals using the other BNCs. The breadboard area can be used to experiment with the circuit shown in Figure 6. Run the software as normal to collect and display the data. The evaluation software uses a normalized scale when displaying data. Figure