PDF《UCC28C4x-EP》

< 2.4 V 0.9

1 1.1 V PSRR Power-supply rejection ratio VDD =

12 V to

18 V(2)(5)

70 dB Input bias current C0.1 C2 ?A CS to output delay

35 70 ns COMP to CS offset VCS =

0 V 1.15 V Output VOUT low (RDS(on) pull-down) ISINK =

200 mA 5.5

15 ? VOUT high (RDS(on) pull-up) ISOURCE =

200 mA

10 25 ? (1) Adjust VDD above the start threshold before setting at

15 V. (2) Not production tested. (3) Output frequencies of the UCC28C41, UCC28C44, and UCC28C45 are one-half the oscillator frequency. (4) Oscillator discharge current is measured with RT =

10 k? to VREF. (5) Parameter measured at trip point of latch with VFB =

0 V.

4 Submit Documentation Feedback Pin Assignments UCC28C4x-EP BiCMOS LOW-POWER CURRENT-MODE PWM CONTROLLERS SGLS352BCDECEMBER 2006CREVISED MAY

2007 Electrical Characteristics (continued) VDD =

15 V, RT =

10 k?, CT = 3.3 nF, CVDD = 0.1 ?F and no load on the outputs, TA = TJ = C55°C to 125°C for the UCC28C4x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rise tIme TA = 25°C, CLOAD =

1 nF

25 50 ns Fall time TA = 25°C, CLOAD =

1 nF

20 40 ns Undervoltage Lockout (UVLO) UCC28C42-EP, UCC28C44-EP 13.5 14.5 15.5 Start threshold UCC28C43-EP, UCC28C45-EP 7.8 8.4

9 V UCC28C40-EP, UCC28C41-EP 6.5

7 7.5 UCC28C42-EP, UCC28C44-EP

8 9

10 Minimum operating voltage UCC28C43-EP, UCC28C45-EP

7 7.6 8.2 V UCC28C40-EP, UCC28C41-EP 6.1 6.6 7.1 PWM UCC28C42-EP, UCC28C43-EP,

94 96 Maximum duty cycle UCC28C40-EP, UCC28C44-EP, %

47 48 UCC28C45-EP, UCC28C41-EP Minimum duty cycle 0% Current Supply ISTART-UP Start-up current VDD = UVLO start threshold (C0.5 V)

50 100 ?A IDD Operating supply current VFB = VCS =

0 V 2.3

3 mA COMP: This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. CS: The current-sense pin is the noninverting input to the PWM comparator. This is compared to a signal proportional to the error amplifier output voltage. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration. FB: This pin is the inverting input to the error amplifier. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%. GND: Ground return pin for the output driver stage and the logic-level controller section. OUT: The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCC28C40, UCC28C42, and UCC28C43 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCC28C41, UCC28C44, and the UCC28C45, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to