PDF《8-bit》

4 8126FSCAVRC05/12 ATtiny13A 2. Overview The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching

1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTER0 INSTRUCTION DECODER DATA DIR. REG.PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER STATUS REGISTER ALU PORT B DRIVERS PB[0:5] VCC GND CONTROL LINES 8-BIT DATABUS Z ADC / ANALOG COMPARATOR INTERRUPT UNIT CALIBRATED Y X RESET CLKI WATCHDOG OSCILLATOR DATA EEPROM

5 8126FSCAVRC05/12 ATtiny13A The AVR core combines a rich instruction set with

32 general purpose working registers. All

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash,

64 bytes EEPROM,

64 bytes SRAM,

6 general purpose I/O lines,

32 general purpose working reg- isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4- channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft- ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Inter- rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel'

s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

6 8126FSCAVRC05/12 ATtiny13A 3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than

1 PPM over

20 years at 85°C or

100 years at 25°C.

7 8126FSCAVRC05/12 ATtiny13A 4. Register Summary Address Name Bit

7 Bit

6 Bit

5 Bit

4 Bit

3 Bit

2 Bit

1 Bit

0 Page 0x3F SREG I T H S V N Z C page

9 0x3E Reserved 0x3D SPL SP[7:0] page