DOC《西安华芯半导体有限公司招聘简章   》

西安华芯半导体有限公司招聘简章??? 西安华芯半导体有限公司,创建于2004年初,原为德国英飞凌存储器事业部,2006年成为奇梦达科技有限公司的西安研发中心.

2009年5月被浪潮集团山东华芯半导体收购,更名并转制成为国有控股的独立公司.公司拥有国内领先、世界同步的集成电路产品设计开发能力,拥有完整先进的集成电路设计软硬件平台以及投资超过一千多万美元的测试中心.公司现有一百五十多名员工,其中包括10名外籍专家、海外留学归国人员和国家 千人计划 专家,具有硕士博士学位人员超过75%. 公司的主营业务是自有品牌存储器产品开发以及先进集成电路设计测试服务.华芯自有品牌大容量DRAM芯片及内存条,广泛应用于服务器、平板电脑、高清电视机顶盒以及工业控制等领域,产品也远销到大陆外的韩国、欧洲、美国等地.基于世界先进工艺的存储器产品设计服务,已成功给包括日本和台湾著名存储器公司开发完成多款大容量高速DRAM产品,同时为国内外多个客户提供了快速准确的存储器测试和失效分析服务.西安华芯还承担有国家 核高基 和

863 计划等多个存储器领域的研究课题和项目,2014年荣获国家 国家规划布局内重点软件企业和集成电路设计企业 . 另外,基于公司先进丰富的集成电路设计测试经验和完善严谨的产品开发流程管理和质量管理,西安华芯也长期给包括美国著名公司提供基于先进工艺的数字电路设计服务. 我们提供先进的设计开发环境,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险.诚邀有志IC事业的人才加盟共同发展! Xi'

an Sinochip Semiconductors can provide advanced design and working environment, competitive salary, perfect vacation system, comprehensive social and commercial insurance system. Welcome to join us! 岗位介绍及要求如下, 有意者请将中文及英文简历发至 [email protected] 职位: 数字后端设计工程师ASIC Backend Design Engineer 上海、西安(急聘!!) 2)Flash电路设计工程师Flash Memory Circuit Design Engineer 3)可测性设计工程师Design for Test Engineer (DFT) 4) 集成电路测试工程师(存储器产品测试工程)IC Product Test Engineer (Memory Product Testing) 5)现场应用工程师Field Applications Engineer 6)集成电路存储器销售主管/经理IC Memory Market and Sales Manager 7)模拟ESD 工程师Analog ESD Engineer 8)设计验证工程师Design and Functional Verification Engineer (DFV) 岗位职责及要求: 1)数字后端设计工程师ASIC Backend Design Engineer (上海、西安)(急聘!!) Responsibilities: 1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route. 2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis. 3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS). 4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization. 5. Static Timing analysis (Prime Time) and setup/hold fix. 6. Formal Verification for equivalence checking (Formality). 7. Generation of fill structures according to technology requirements. Requirements: 1. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus. 4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus. 5. Good analytical and debugging skills. 6. Good command of English. 2)Flash电路设计工程师Flash Memory Circuit Design Engineer Responsibility: 1.Design and simulation of Flash memory at deep sub-micron process node including row and column decoding, read/program/erase control circuits and read sense amplifier etc. 2.Verify the function and performance of FLASH memory at block-level and full-chip level. 3.Floor-planning FLASH chip architecture. 4.Work closely with layout engineer, provide layout guide line, and check the layout quality. 5.Analysis chip'