PDF《Flip-Flops》

DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or rela- tively low-impedance loads.

The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter- face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM54/74LS373 are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up. The eight flip-flops of the DM54/74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are off. Features n Choice of

8 latches or

8 D-type flip-flops in a single package n 3-STATE bus-driving outputs n Full parallel-access for loading n Buffered control inputs n P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages 'LS373 DS006431-1 Order Number DM54LS373J, DM54LS373W, DM74LS373N or DM74LS373WM See Package Number J20A, M20B, N20A or W20A March

1998 DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops ?

1998 Fairchild Semiconductor Corporation DS006431 www.fairchildsemi.com Connection Diagrams (Continued) Function Tables DM54/74LS373 Output Enable D Output Control G L H H H L H L L L L X Q0 H X X Z H = High Level (Steady State), L = Low Level (Steady State), X = Don't Care ↑ = Transition from low-to-high level, Z = High Impedance State Q0 = The level of the output before steady-state input conditions were estab- lished. DM54/74LS374 Output Clock D Output Control L ↑ H H L ↑ L L L L X Q0 H X X Z 'LS374 DS006431-2 Order Number DM54LS374J, DM54LS374W, DM74LS374WM or DM74LS374N See Package Number J20A, M20B, N20A or W20A www.fairchildsemi.com

2 Logic Diagrams DM54/74LS334 Transparent Latches DS006431-3 DM54/74LS374 Positive-Edge-Triggered Flip-Flops DS006431-4

3 www.fairchildsemi.com Absolute Maximum Ratings (Note 1) Supply Voltage 7V Input Voltage 7V Storage Temperature Range ?65?C to +150?C Operating Free Air Temperature Range DM54LS ?55?C to +125?C DM74LS 0?C to +70?C Recommended Operating Conditions Symbol Parameter DM54LS373 DM74LS373 Units Min Nom Max Min Nom Max VCC Supply Voltage 4.5

5 5.5 4.75

5 5.25 V VIH High Level Input Votage

2 2 V VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current ?1 ?2.6 mA IOL Low Level Output Current

12 24 mA tW Pulse Width Enable High

15 15 ns (Note 3) Enable Low

15 15 tSU Data Setup Time (Notes 2, 3) 5↓ 5↓ ns tH Data Hold Time (Notes 2, 3) 20↓ 20↓ ns TA Free Air Operating Temperature ?55

125 0

70 ?C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25?C and VCC = 5V. 'LS373 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 4) VI Input Clamp Voltage VCC = Min, II = ?18 mA ?1.5 V VOH High Level Output Voltage VCC = Min DM54 2.4 3.4 IOH = Max V VIL = Max DM74 2.4 3.1 VIH = Min VOL Low Level Output Voltage VCC = Min DM54 0.25 0.4 IOL = Max VIL = Max DM74 0.35 0.5 V VIH = Min IOL =

12 mA DM74 0.4 VCC = Min II Input Current @ Max VCC = Max, VI = 7V 0.1 mA Input Voltage IIH High Level Input Current VCC = Max, VI = 2.7V

20 ?A IIL Low Level Input Current VCC = Max, VI = 0.4V ?0.4 mA IOZH Off-State Output Current VCC = Max, VO = 2.7V with High Level Output VIH = Min, VIL = Max

20 ?A Voltage Applied IOZL Off-State Output Current VCC = Max, VO = 0.4V with Low Level Output VIH = Min, VIL = Max ?20 ?A Voltage Applied IOS Short Circuit VCC = Max DM54 ?20 ?100 mA Output Current (Note 5) DM74 ?50 ?225 www.fairchildsemi.com

4 'LS373 Electrical Characteristics (Continued) over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 4) ICC Supply Current VCC = Max, OC = 4.5V,

24 40 mA Dn, Enable = GND 'LS373 Switching Characteristics at VCC = 5V and TA = 25?C From RL = 667? Symbol Parameter (Input) CL =

45 pF CL =

150 pF Units To Min Max Min Max (Output) tPLH Propagation Delay Data Time Low to High to

18 26 ns Level Output Q tPHL Propagation Delay Data Time High to Low to

18 27 ns Level Output Q tPLH Propagation Delay Enable Time Low to High to

30 38 ns Level Output Q tPHL Propagation Delay Enable Time High to Low to

30 36 ns Level Output Q tPZH Output Enable Output Time to High Control

28 36 ns Level Output to Any Q tPZL Output Enable Output Time to Low Control

36 50 ns Level Output to Any Q tPHZ Output Disable Output Time from High Control

20 ns Level Output (Note 6) to Any Q tPLZ Output Disable Output Time from Low Control

25 ns Level Output (Note 6) to Any Q Note 4: All typicals are at VCC = 5V, TA = 25?C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: CL =

5 pF. Recommended Operating Conditions Symbol Parameter DM54LS374 DM74LS374 Units Min Nom Max Min Nom Max VCC Supply Voltage 4.5

5 5.5 4.75

5 5.25 V VIH High Level Input Voltage

2 2 V VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current ?1 ?2.6 mA IOL Low Level Output Current

12 24 mA

5 www.fairchildsemi.com Recommended Operating Conditions (Continued) Symbol Parameter DM54LS374 DM74LS374 Units Min Nom Max Min Nom Max tW Pulse Width Clock High

15 15 ns (Note 8) Clock Low

15 15 tSU Data Setup Time (Notes 7, 8) 20↑ 20↑ ns tH Data Hold Time (Notes 7, 8) 1↑ 1↑ ns TA Free Air Operating Temperature ?55

125 0

70 ?C Note 7: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25?C and VCC = 5V. 'LS374 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 9) VI Input Clamp Voltage VCC = Min, II = ?18 mA ?1.5 V VOH High Level Output Voltage VCC = Min DM54 2.4 3.4 IOH = Max DM74 2.4 3.1 V VIL = Max VIH = Min VOL Low Level Output Voltage VCC = Min DM54 0.25 0.4 IOL = Max DM74 0.35 0.5 VIL = Max V VIH = Min IOL =

12 mA DM74 0.25 0.4 VCC = Min II Input Current @ Max VCC = Max, VI = 7V 0.1 mA Input Voltage IIH High Level Input Current VCC = Max, VI = 2.7V

20 ?A IIL Low Level Input Current VCC = Max, VI = 0.4V ?0.4 mA IOZH Off-State Output VCC = Max, VO = 2.7V Current with High VIH = Min, VIL = Max

20 ?A Level Output Voltage Applied IOZL Off-State Output VCC = Max, VO = 0.4V Current with Low VIH = Min, VIL = Max ?20 ?A Level Output Voltage Applied IOS Short Circuit VCC = Max DM54 ?50 ?225 mA Output Current (Note 10) DM74 ?50 ?225 ICC Supply Current VCC = Max, Dn = GND, OC = 4.5V

27 45 mA www.fairchildsemi.com

6 'LS374 Switching Characteristics at VCC = 5V and TA = 25?C RL = 667? Symbol Parameter CL =

45 pF CL =

150 pF Units Min Max Min Max fMAX Maximum Clock Frequency

35 20 MHz tPLH Propagation Delay Time

28 32 ns Low to High Level Output tPHL Propagation Delay Time

28 38 ns High to Low Level Output tPZH Output Enable Time

28 44 ns to High Level Output tPZL Output Enable Time

28 44 ns to Low Level Output tPHZ Output Disable Time

20 ns from High Level Output (Note 11) tPLZ Output Disable Time

25 ns from Low Level Output (Note 11) Note 9: All typicals are at VCC = 5V, TA = 25?C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 11: CL =

5 pF.

7 www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS373J or DM54LS374J Package Number J20A 20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS373WM or DM74LS374WM Package Number M20B www.fairchildsemi.com

8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS373N and DM74LS374N Package Number N20A 20-Lead Ceramic Flat Package (W) Order Number DM54LS373W or DM54LS374W Package Number W20A

9 www.fairchildsemi.com LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 www.fairchildsemi.com Fairchild Semiconductor Europe Fax: +49 (0)

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85 86 Email: [email protected] Deutsch Tel: +49 (0)

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5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre,

5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.