PDF《Block Diagram》

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1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION

2 NOTES: Title, Notes, Block Diagram, Revision History

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5 6 Digital Ground

938 Parts,

61 Library Parts,

803 Nets,

4689 Pins B-1 8/13/2007 ALL Release B-1 Cyclone III F780 Development Kit Host Block Diagram 1.

Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework C3 FPGA Package Top 2. 100-0310703-D1 110-0310703-D1 120-0310703-D1 130-0310703-D1 140-0310703-D1 150-0310703-D3 160-0310703-D1 170-0310703-D1 180-0310703-D1 210-0310703-D1 220-0310703-D1 320-0310703-D1

26 27 Power

1 Power

2 Current Sense Cyclone III Power Cyclone III Clocks MAX II DDR2 SDRAM (x72) DDR2 SDRAM POWER &

TERM SRAM &

FLASH USB 2.0 10/100/1000 Ethernet HSM Connectors User IO &

Connector Cyclone III Configuration Cyclone III Banks 1,2,5&

6 Cyclone III Banks 3,4,7&

8 Decoupling HSM Termination C-1 10/2/2007 ALL Moved C507 to pwr instead of gnd, Changed D35 to 40V schottky, Routed DEV_SEL &

JTAG_SEL jumper signals back to MAXII, Changed VCCA and VCCD PLL power decoupling, Changed R35,R38 to DNI, Changed CPU_RESETn pullup to 2.5V and changed MAXII pin to 2.5V bank, Changed current sense circuit completely to version from SIII Host Board and added more measurements, Moved several MAXII pins to accomodate more 2.5V signals to power measurement circuit. Changed OLED display connector to DNI, Increased output and coupling caps on -12V reg D-1 10/9/2007 3,4,5 Changed U36,U37,C79,R85,C78,C478,R227,R228 C247-248, R140 to DNI (do not install), shorted pins

1 to

5 on U36, shorted pins

1 to

3 on U37. Changed R13,R24,R28,R32,R43,R44,R46,R48,R49,R51,R80,R81,R134 from 3mohm to 9mohm. Changed LTC1865L to LTC2402 (24-bits). Added pullup to LCD_SERn. Change the R54-R56, R60-62, and R77-R79 part number from

220 ohm reistors to

0 ohm resistors to match the BOM. D-2

16 10/2/2008

16 D-3 12/3/2008 Change R61 from

0 ohm to

220 ohm. 1,4,12 E-1 5/20/2011 Change bias voltages V1,V2,V3,V4,V5 to positive voltages and remove -12V regulator circuit. LCD changed from F-51852 series to F-55472 series. Depopulated U9 Cypress USB Device Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

1 20 Saturday, May 28,

2011 150-0310703-E1 (6XX-40264R) Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

1 20 Saturday, May 28,

2011 150-0310703-E1 (6XX-40264R) Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

1 20 Saturday, May 28,

2011 150-0310703-E1 (6XX-40264R) Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved.

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1 1 E E D D C C B B A A BANK

7 (A) (L) 1. BANK

3 (K) Notes: BANK

6 (B) Bank

5 - HSMB VCCIO = 1.8V VCCIO = 2.5V FPGA Schematic Symbol Breakdown: VCCIO, VREF (I) (F) Bank

2 - ENET, HSMA, LCD (H) VCCINT, VCCA BANK

5 BANK

8 (J) BANK

4 Bank

4 - DDR2 SDRAM, FLASH, FSA, SRAM, USER I/O VCCIO = 1.8V (D) (C) VCCIO = 2.5V (E) (G) VCCIO = 1.8V VCCIO = 1.8V Cyclone III FPGA Package Top (M) (N) Bank

3 - DDR2 SDRAM,FSA, HSMA (CLKIN), SRAM, USER I/O Some Clocks Bank

1 - ENET,HSMA, LCD Bank

6 - HSMB, LCD, USB (O) Configuration Ground Ground and NCs Ground VCCIO = 2.5V BANK

1 BANK

2 VCCIO = 2.5V Bank

8 - DDR2 SDRAM, FSD, SRAM, USER I/O Bank

7 - DDR2 SDRAM, FSD, HSMB (CLKIN), MAX, USER I/O Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

2 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

2 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

2 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved.

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1 1 E E D D C C B B A A Power

1 14V-20V DC INPUT POWER LED LTM_FB POWER_GOOD RUN_SW PG_12V PG_12V LT1761_ADJ PG_12V PG_12V LTM_FB FSET MPGM DC_INPUT 3.3V DC_INPUT 3.3V 3.3V DC_INPUT 12V 5.0V 12V 3.3V 5.0V_OUT 12V_OUT 12V 3.3V_OUT POWER_GOOD 4,5 PG_12V Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

3 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

3 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of D-3 Cyclone III Development Kit Host Board B

3 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. C11 1000pF C11 1000pF D9 B520C-13 D9 B520C-13

2 1 R134 .009 R134 .009 R6 13.3K R6 13.3K R29 10.0K R29 10.0K U1D LTM4601 U1D LTM4601 INTVCC A7 PLLIN A8 TRACK/SS A9 RUN A10 FSET B12 MARG0 C12 MARG1 D12 VFB F12 PGOOD G12 DRVCC E12 COMP A11 MPGM A12 VOSNS+ J12 VOSNS- M12 VOUT_LCL L12 DIFFVOUT K12 R122 100, 1% R122 100, 1% C14 100uF C14 100uF C5 10uF C5 10uF C236 4.7uF C236 4.7uF R28 .009 R28 .009 + C25 10V Tantalum 470uF + C25 10V Tantalum 470uF

1 2 U1A LTM4601 U1A LTM4601 VOUT J1 VOUT J2 VOUT J3 VOUT J4 VOUT J5 VOUT J6 VOUT J7 VOUT J8 VOUT J9 VOUT J10 VOUT K1 VOUT K2 VOUT K3 VOUT K4 VOUT K5 VOUT K6 VOUT K7 VOUT K8 VOUT K9 VOUT K10 VOUT K11 VOUT L1 VOUT L2 VOUT L3 VOUT L4 VOUT L5 VOUT L6 VOUT L7 VOUT L8 VOUT L9 VOUT L10 VOUT L11 VOUT M1 VOUT M2 VOUT M3 VOUT M4 VOUT M5 VOUT M6 VOUT M7 VOUT M8 VOUT M9 VOUT M10 VOUT M11 R22 10.0K R22 10.0K C237 4.7uF C237 4.7uF L3 10uH L3 10uH

1 2 + C35 25V Tantalum 22uF + C35 25V Tantalum 22uF

1 2 R13 .009 R13 .009 U1B LTM4601 U1B LTM4601 PGND D1 PGND D2 PGND D3 PGND D4 PGND D5 PGND D6 PGND E1 PGND E2 PGND E3 PGND E4 PGND E5 PGND E6 PGND E7 PGND F1 PGND F2 PGND F3 PGND F4 PGND F5 PGND F6 PGND F7 PGND F8 PGND F9 PGND G1 PGND G2 PGND G3 PGND G4 PGND G5 PGND G6 PGND G7 PGND G8 PGND G9 PGND H1 PGND H2 PGND H3 PGND H4 PGND H5 PGND H6 PGND H7 PGND H8 PGND H9 SGND H12 C29 1000pF C29 1000pF D5 Blue_Led D5 Blue_Led C89 47nF C89 47nF U14 LT1761 U14 LT1761 VIN

1 GND

2 VOUT

5 ADJ/BYPASS

4 SHDN

3 R9 1.00k R9 1.00k C210 0.22uF C210 0.22uF C6 1000pF C6 1000pF C7 100pF C7 100pF D34 FM540 D34 FM540 C4 10uF C4 10uF C19 150u C19 150u SW2 EG2201A SW2 EG2201A

1 2

3 6

5 4 R26 845K R26 845K R3 787K R3 787K U10 LT3481 U10 LT3481 BD

1 SW

3 RUN/SS

5 VIN

4 BOOST

2 PG

6 BIAS

7 FB

8 VC

9 RT

10 GND

11 R31 3.24K R31 3.24K C30 330pF C30 330pF R5 100K R5 100K R23 78.7K R23 78.7K C1 0.01uF C1 0.01uF C15 100uF C15 100uF R4 100K R4 100K R25 30.1K R25 30.1K R27 100K R27 100K D2 20V Zener D2 20V Zener C209 10uF C209 10uF J2 RAPC712X J2 RAPC712X

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1 U1C LTM4601 U1C LTM4601 VIN A1 VIN A2 VIN A3 VIN A4 VIN A5 VIN A6 VIN B1 VIN B4 VIN B5 VIN B6 VIN C1 VIN C2 VIN C3 VIN C4 VIN C5 VIN B2 VIN B3 VIN C6

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1 1 E E D D C C B B A A Power

2 0.9V VTT (3A Sink/Src) CIII BANKS

1 &

2 CIII BANKS

5 &

6 Graphics LCD Backlight Power Header (Hook black wire to pin 2) CIII PLL ANALOG POWER Other 2.5V (non-FPGA) CIII PLL DIGITAL POWER RED Above power circuit was reworked to support a new graphics LCD with +12V bias voltages, not the original -12V voltages. 9.3V Short 12V to old -12V rail for new positive bias voltage LCD 8.3V 7.3V 2.1V 1.0V 12V FOR USE WITH NEW LCDF-55472 Series ONLY (old -12V circuit for use only with F-51852 Series ONLY) POWER_GOOD POWER_GOOD POWER_GOOD 1.8V_SW 1.8V_VFB 1.2V_VFB POWER_GOOD -12SW +12SW BLACK -12FB POWER_GOOD VREF_B3_B4 VTT_B3_B4 5.0V 1.8V 3.3V 2.5V_B1_B2 3.3V 2.5V_B5_B6 2.5V_OUT 3.3V 1.2V_OUT 1.2V_INT 1.8V VREF_B7_B8 VTT_B7_B8 5.0V 1.8V 1.8V_B3_B4 1.8V_B7_B8 12V V4 V3 V2 V5 V1 2.5V 1.2V_VCCD 3.3V 1.2V_PLL 1.2V 2.5V 2.5V_VCCA 1.8V_OUT POWER_GOOD 3,5 Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

4 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

4 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, CA

92121 Copyright (c) 2008, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of E-1 Cyclone III Development Kit Host Board B

4 20 Saturday, May 28,

2011 150-0310703-D3 Altera Corporation,

9330 Scranton Rd #400, San Diego, C........