PDF《LPS001D》

14 Table 7. Serial interface pin description

14 Table 8. SAD+read/write patterns.15 Table 9. Transfer when master is writing one byte to slave

15 Table 10. Transfer when master is writing multiple bytes to slave

16 Table 11. Transfer when master is receiving (reading) one byte of data from slave

16 Table 12. Transfer when master is receiving (reading) multiple bytes of data from slave

16 Table 13. Register address map.20 Table 14. WHO_AM_I (0Fh) register

21 Table 16. CTRL_REG1 (20h) register description

21 Table 17. Output data rate bit configurations

22 Table 18. CTRL_REG2 (21h) register

22 Table 19. CTRL_REG2 (21h) register description

22 Table 20. CTRL_REG3 [Interrupt CTRL register] (22h) register.23 Table 21. CTRL_REG3 [Interrupt CTRL register] (22h) register description

23 Table 22. Data signal on INT1(2) pad control bits

23 Table 23. STATUS_REG (27h) register

24 Table 24. STATUS_REG (27h) register description

24 Table 25. PRESS_OUT_L (28h) register

24 Table 26. PRESS_OUT_L (28h) register description

24 Table 27. PRESS_OUT_H (29h) register

25 Table 28. PRESS_OUT_H (29h) register description.25 Table 29. TEMP_OUT_L (2Ah) register

25 Table 30. TEMP_OUT_L (2Ah) register description

25 Table 31. TEMP_OUT_H (2Bh) register.25 Table 32. TEMP_OUT_H (2Bh) register description.26 Table 33. DELTA_P_L (2Ch) register.26 Table 34. DELTA_P_L (2Ch) register description

26 Table 35. DELTA_P_H (2Dh) register

26 Table 36. DELTA_P_H (2Dh) register description

26 Table 37. REF_P_L (30h) register

26 Table 38. REF_P_L (30h) register description

27 Table 39. REF_P_H (31h) register

27 Table 40. REF_P_H (31h) register description.27 Table 41. THS_P_L (32h) register

27 Table 42. THS_P_L (32h) register description

27 Table 43. THS_P_H (33h) register

27 Table 44. THS_P_H (33h) register description.28 Table 45. INTERRUPT_CFG (34h) register

28 Table 46. INTERRUPT_CFG (34h) register description.28 Table 47. INT_SOURCE (35h) register

28 Table 48. INT_SOURCE (35h) register description

28 Table 49. INT_ACK (36h) register

29 Table 50. Document revision history

31 LPS001D List of figures Doc ID

17726 Rev

1 5/32 List of figures Figure 1. Block diagram

6 Figure 2. Pin connection

6 Figure 3. Interrupt generation block and output pressure data.11 Figure 4. LPS001D electrical connection.13 Figure 5. Read and write protocol

17 Figure 6. SPI read protocol

17 Figure 7. Multiple bytes SPI read protocol (2 byte example)18 Figure 8. SPI write protocol

18 Figure 9. Multiple bytes SPI write protocol (2 byte example)19 Figure 10. SPI read protocol in 3-wires mode

19 Figure 11. HLGA 5x5 16L: mechanical data and package dimensions

30 Block diagram and pin information LPS001D 6/32 Doc ID

17726 Rev

1 1 Block diagram and pin information Figure 1. Block diagram Figure 2. Pin connection Table 2. Pin description Pin # Pin Name Function

1 CS SPI enable I2C/SPI mode selection (logic 1: I2C mode;

logic 0: SPI enabled)

2 SCL/SPC I2C serial clock (SCL) SPI serial port clock (SPC) p MUX

16 BIT Σ? ADC D S P FOR LOW NOI S E DIGITAL FILTER TEMPERATURE COMPEN S ATION ANALOG FRONT END I2 C CS SENSOR BIAS TEMPERATURE SENSOR VOLTAGE AND CURRENT BIAS CLOCK TIMING SPI SCL/SPC SDA/SDO/SDI SA0/SDO + Vup Vdown Vout Rs Rs Rs Rs SENSING ELEMENT AND AM07299v1 Re s erved BOTTOM VIEW Vdd Vdd Vdd_IO GND Reserved Reserved GND Re s erved INT2 INT1 SA0/SDO SDA/SDI/SDO GND SCL/SPC CS Pin

1 indicator

1 1

5 6

16 8

9 13

14 Pin

1 Indicator AM07300v1 LPS001D Block diagram and pin information Doc ID