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4 个L3 地址过滤器(Ipv6) ?

4 个L2 地址过滤器 Net-Swift ,Inc SP1000A datasheet

4 1.1.7 接口 ?

10 Gb 双端口设备或单端口 ? PCIe Gen3,总线宽度――x1,x2,x4,x8 ? 每个 LAN 端口

8 个GPIO 引脚 ? 每个 LAN 端口

1 个IIC ? SPI 闪存接口 ? UART 接口 ? NCSI 端口 ?

8 GPIO 引脚 ? SMbus 端口 ? 设备禁用功能 1.2 引脚描述 Note: the single-ended signal IO level standard of SP1000A chip is 1.8V LVCMOS standard. Table1:Chip status Ball # Pin Name Type Description H5 PCIE_BSY Output Active-High Asserted when PCI Express link has traffic B1 ETH_UP_1 Asserted when Ethernet port1 is UP C1 ETH_1G_0 Asserted when Ethernet port0 is at 1Gbps D1 ETH_100M_0 Asserted when Ethernet port0 is at 100Mbps E1 ETH_BSY_1 Asserted when Ethernet port1 has traffic A2 ETH_10G_0 Asserted when Ethernet port0 is at 10Gbps B2 ETH_BSY_0 Asserted when Ethernet port0 has traffic C2 ETH_10G_1 Asserted when Ethernet port1 is at 10Gbps D2 ETH_100M_1 Asserted when Ethernet port1 is at 100Mbps E2 ETH_UP_0 Asserted when Ethernet port0 is UP G4 ETH_1G_1 Asserted when Ethernet port1 is at 1Gbps G5 MNG_BSY Asserted when on-chip has traffic. Net-Swift ,Inc SP1000A datasheet

5 Table2:Chip Control Ball # Pin Name Type Description M1 PORST_N Input Active-Low power-on reset J4 PLL_BYPASS Active-High. If asserted, Internal PLL is bypassed. It should not be asserted for normal operation. J5 PLL_REF_CLK 50MHz PLL reference clock. M5 LAN1_DIS_N Active-Low. If asserted, Ethernet port0 is disabled. M2 FLASH_BYPASS Active-High. If asserted, off-chip flash is bypassed, pre-configuration is NOT loaded. R1 LAN2_DIS_N Active-Low. If asserted, Ethernet port1 is disabled. G2 MNG_DET Active-High. If asserted, on-chip CPU is enabled. W2 SEC_DISABLE Active-High. If asserted, LinkSec and IPsec are disabled. Y21 FLASH_SECTOR

0 means image1 starts at 64KB address,

1 means image1 starts at 256KB address. T4 SEC_MODE Active-High. If asserted, host CPU can'

t access on-chip CPU registers. H3 PCIE_PHY_PARA_SEL Active-High. If asserted, PHY Internal registers are accessed by Internal logic, otherwise PHY Internal registers are accessed by JTAG. H1 ETH_PHY_PARA_SEL G1 ETH_PHY_SRAM_BYPASS Active-High. If asserted, PHY Internal SRAM is bypassed. H4 PCIE_PHY_SRAM_BYPASS T5 PE_RST_SEQ Active-High. If asserted, SP assumes power-on-reset removal before that of PERST. It is Internally pull-down, could be floating Input board design. L5 PE_AUX_PWR_DET Active-High when chip has Auxiliary power supply. U9 PE_PHY0_RESREF Connect to 200Ω (±1%) off-chip resistor for PHY Internal calibration. U13 PE_PHY1_RESREF F7 ETH0_RESREF F15 ETH1_RESREF Net-Swift ,Inc SP1000A datasheet

6 Table3:Ethernet Port0 PHY Ball # Pin Name Type Description A4 ETH0_RX_N_0 Input CML differential signal, Ethernet Port0 PHY differential pairs, ETH0_RX_0 differential pair for connection to SFI RX, ETH0_TX_0 differential pair for connection to SFI TX. B4 ETH0_RX_P_0 Input D4 ETH0_TX_N_0 Output E4 ETH0_TX_P_0 Output A6 ETH0_RX_N_1 Input B6 ETH0_RX_P_1 Input D6 ETH0_TX_N_1 Output E6 ETH0_TX_P_1 Output A8 ETH0_RX_N_2 Input B8 ETH0_RX_P_2 Input D8 ETH0_TX_N_2 Output E8 ETH0_TX_P_2 Output A10 ETH0_RX_N_3 Input B10 ETH0_RX_P_3 Input D10 ETH0_TX_N_3 Output E10 ETH0_TX_P_3 Output F9 ETH0_REF_CLK_N Input Ethernet Port0 156.25MHz reference clock, LVDS level Input. G9 ETH0_REF_CLK_P Table4:Ethernet Port1 PHY Ball # Pin Name Type Description A18 ETH1_RX_N_0 Input CML differential........