PDF《AMD Bolton FCH》

16 2.3 MMIO Programming for Legacy Devices

16 2.4 Enable Boot Timer

17 2.5 RTC Wake Up

17 2.6 Keyboard Reset Settings for Legacy Free Systems

18 2.7 NB Power Good Control on System Reset

18 2.8 Enhancement of FanOut0 Control

18 2.9 Extend SerIrq Request

19 2.10 Mt C1e Enable

19 2.11 HWM Sensor CLK

19 2.12 Clear Status of SATA PERR

20 2.13 Enable Delayed SLP_S3/S5 to Motherboard

20 2.14 Enable C-State Wake-up before Warm Reset

20 2.15 Enable DMAACTIVE#20 2.16 IMC Enable

21 2.17 Adjust PM Timer Read Mechanism

21 2.18 PCIe? Wake Status and PME Wake Status

21 2.19 Set RTC OSC Output Drive

21 3 LPC Controller (bus-0, dev-20, fun-3)23 3.1 SPI Controller MMIO Base Address

23 3.2 Enable SPI ROM Prefetch

23 3.3 Enable LPC DMA Function

23 3.4 Enable ClkRun Function

24 3.5 Enable LPCCLK0 Power-Down Function

24 3.6 Disable LPC A-Link Cycle Bypass

24 3.7 LPC Cycle Abort Sync Threshold Setting

24 4 UMI and A/B-Link Settings - Indirect I/O Access

25 4.1 Defining AB_REG_BAR

25 4.2 Upstream DMA Access

25 4.3 PCIB Prefetch Settings

25 4.4 OHCI Prefetch Settings

26 4.5 B-Link Client'

s Credit Variable Settings for the Downstream Arbitration Equation

26 4.6 Setting B-Link Prefetch Mode

26 4.7 Detection of Upstream Interrupts

26 51191 AMD Bolton Register Programming Requirements Rev 3.00 ?

2014 Advanced Micro Devices, Inc. Page

8 4.8 Downstream Posted Transactions to Pass Non-Posted Transactions

27 4.9 AB and UMI/GPP Clock Gating

27 4.10 AB Int_Arbiter Enhancement

27 4.11 Requester ID

27 4.12 UMI LOs/L1 NAK Reduction

28 4.13 Power Saving Feature for UMI Lanes.28 4.14 Non-Posted Memory Write Support

28 4.15 SMI Ordering

29 4.16 Posted Pass Non-Posted Feature

29 4.17 UMI Speed Change

29 4.18 UMI L1 Configuration

30 5 PCIe? General Purpose Ports

31 5.1 GPP Lane Configuration

31 5.2 GPP Port 0/1/2/3

31 5.3 GPP Reset

32 5.4 PCIe? Ports De-emphasis Settings

33 5.5 Write Capability for PCIe? Read-Only Registers

33 5.6 Serial Number Capability

34 5.7 Multi-function Enable

34 5.8 GPP Upstream Memory Write Arbitration Enhancement

34 5.9 GPP Memory Write Max Payload Improvement

34 5.10 Multiple GPP Device Support

35 5.11 Separate Control for Release from Reset and Hold Training for each GPP Port

35 5.12 GPP PCIe? Native Interrupt Support

35 5.13 GPP Error Reporting Configuration

36 5.14 Hot Plug: PCIe? Native Support

36 5.15 Link Bandwidth Notification Capability Enable

36 5.16 Power Saving Feature for GPP Lanes

37 5.17 GPP L1 PM Request NAK Reduction

37 5.18 GPP ASPM L1/L0s Enable

38 5.19 GPP Immediate Ack PM_Active_State_Request_L1

38 5.20........