PDF《STM32F303xD STM32F303xE Errata sheet》

17 2.9 USART peripheral limitations

17 2.9.1 Start bit detected too soon when sampling for NACK signal from the Smartcard

17 2.9.2 A break request can prevent the Transmission Complete flag (TC) from being set

17 2.9.3 nRTS is active while RE =

0 or UE =

0 18 2.9.4 Receiver timeout counter starting in case of

2 stop bits configuration . .

18 2.10 FMC limitations

18 2.10.1 Dummy read cycles inserted when reading synchronous memories . . .

18 2.10.2 Data corruption during burst read from FMC synchronous memory . . .

18 2.10.3 FMC bank switching to asynchronous bank for write

19 3 Revision history

20 List of tables STM32F303xD STM32F303xE 4/21 ES0261 Rev

5 List of tables Table 1. Device identification

1 Table 2. Device summary

1 Table 3. Cortex? -M4 core with FPU limitations and impact on microcontroller behavior

5 Table 4. Summary of silicon limitations

7 Table 5. Document revision history

20 ES0261 Rev

5 5/21 STM32F303xD STM32F303xE Arm? 32-bit Cortex?-M4 core with FPU limitations

20 1 Arm? 32-bit Cortex?-M4 core with FPU limitations For information on the Arm?(a) Cortex?-M4 core, please refer to the Cortex?-M4 technical reference manual, available from the www.arm.com website. All the described limitations are minor and related to the revision r0p1-v1 of the Cortex?-M4 core with FPU. Table

3 summarizes these limitations and their implications on the behavior of the STM32F30xxx devices. 1.1 Cortex?-M4 core with FPU interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring durin........