PDF《LM25101 3A、2A 和1A 80V 半桥栅极驱动器》

5 Changes from Original (March 2013) to Revision A Page ? 已更改 国家半导体数据表的布局至 TI 格式

1 3 LM25101 www.ti.com.cn ZHCSFK2C CJULY 2012CREVISED SEPTEMBER

2016 Copyright ? 2012C2016, Texas Instruments Incorporated

5 Device Options Table 1. Input/Output Options Part Number Input Thresholds Peak Output Current LM25101A TTL

3 A LM25101B TTL

2 A LM25101C TTL

1 A

6 Pin Configuration and Functions DGN and DDA Packages 8-Pin MSOP and SO PowerPAD Top View NGT Package 8-Pin WSON Top View D Package 8-Pin SOIC Top View DPR Package 10-Pin WSON Top View

4 LM25101 ZHCSFK2C CJULY 2012CREVISED SEPTEMBER

2016 www.ti.com.cn Copyright ? 2012C2016, Texas Instruments Incorporated (1) TI recommends that the exposed thermal pad on the bottom of the applicable packages is soldered to ground plane of the PCB, and the ground plane should extend out from beneath the IC to help dissipate heat. Pin Functions PIN TYPE DESCRIPTION NAME MSOP PowerPAD WSON (8) WSON (10) SO PowerPAD SOIC HB

2 2

2 2

2 PWR High-side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible. HI

5 5

7 5

5 I High-side driver control input. The LM25101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. HO

3 3

3 3

3 O High-side gate driver output. Connect to the gate of high-side MOSFET with a short, low inductance path. HS

4 4

4 4

4 GND High-side MOSFET source connection. Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. LI

6 6

8 6

6 I Low-side driver control input. The LM25101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. LO

8 8

10 8

8 O Low-side gate driver output. Connect to the gate of the low-side MOSFET with a short, low inductance path. NC ― ― 5,

6 ― ― ― No connection VDD

1 1

1 1

1 PWR Positive gate drive supply. Locally decouple to VSS using a low ESR and ESL capacitor located as close to the IC as possible. VSS

7 7

9 7

7 GND Ground return. All signals are referenced to this ground. Thermal Pad PowerPAD Thermal Pad Thermal Pad PowerPAD ― ― Solder to the ground plane under the IC to aid in heat dissipation.(1) (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For performance limits and associated test conditions, see the Electrical Characteristics tables. (2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed C1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD C

15 V. For example, if VDD =

10 V, the negative transients at HS must not exceed C5 V.

7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD to VSS ?0.3

18 V HB to HS ?0.3

18 V LI or HI Input ?0.3 VDD + 0.3 V LO Output ?0.3 VDD + 0.3 V HO Output VHS - 0.3 VHB + 0.3 V HS to VSS(2) C5