PDF《14-Bit, 125/105/80Msps》

1 For more information www.

linear.com/LTC2261-14 Typical Application Features Applications Description 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing n 73.4dB SNR n 85dB SFDR n Low Power: 127mW/106mW/89mW n Single 1.8V Supply n CMOS, DDR CMOS or DDR LVDS Outputs n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full-Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm * 6mm) QFN Package The LTC? 2261-14/LTC2260-14/LTC2259-14 are sam- pling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performancethatincludes73.4dBSNRand85dBspurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance. DCspecsinclude±1LSBINL(typical),±0.3LSBDNL(typi- cal)andnomissingcodesovertemperature.Thetransition noise is a low 1.2LSBRMS. The digital outputs can be either full-rate CMOS, double- data rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENCC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 2-Tone FFT, fIN = 70MHz and 75MHz C + INPUT S/H CORRECTION LOGIC OUTPUT DRIVERS 14-BIT PIPELINED ADC CORE CLOCK/DUTY CYCLE CONTROL D13 ? ? ? D0 125MHz CLOCK ANALOG INPUT

226114 TA01a CMOS OR LVDS 1.2V TO 1.8V 1.8V VDD OVDD OGND GND FREQUENCY (MHz)

0 C100 C110 C120 C70 C60 C80 C90 AMPLITUDE (dBFS) C50 C30 C40 C20 C10

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60 226114 TA01b L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

2 For more information www.linear.com/LTC2261-14 Absolute Maximum Ratings Supply Voltages (VDD, OVDD)0.3V to 2V Analog Input Voltage (AIN +, AIN C, PAR/SER, SENSE) (Note 3)0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENCC, CS, SDI, SCK) (Note 4)0.3V to 3.9V SDO (Note 4)0.3V to 3.9V (Notes 1, 2)

39 40

38 37

36 35

34 33

32 31

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12 13

14 15 FULL-RATE CMOS OUTPUT MODE TOP VIEW

41 GND UJ PACKAGE 40-LEAD (6mm * 6mm) PLASTIC QFN

16 17

18 19

22 23

24 25

26 27

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9 8

7 6

5 4

3 2 AIN + AIN C GND REFH REFH REFL REFL PAR/SER VDD VDD D9 D8 CLKOUT+ CLKOUTC OVDD OGND D7 D6 D5 D4 V DD SENSE V REF V CM OF DNC D13 D12 D11 D10 ENC + ENC C CS SCK SDI SDO D0 D1 D2 D3

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10 1 TJMAX = 150°C, θJA = 32°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

39 40

38 37

36 35

34 33

32 31

11 20

12 13

14 15 DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW

41 GND UJ PACKAGE 40-LEAD (6mm * 6mm) PLASTIC QFN

16 17

18 19

22 23

24 25

26 27

28 29

9 8

7 6

5 4

3 2 AIN + AIN C GND REFH REFH REFL REFL PAR/SER VDD VDD D8_9 DNC CLKOUT+ CLKOUTC OVDD OGND D6_7 DNC D4_5 DNC V DD SENSE V REF V CM OF DNC D12_13 DNC D10_11 DNC ENC + ENC C CS SCK SDI SDO DNC D0_1 DNC D2_3

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10 1 TJMAX = 150°C, θJA = 32°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB