PDF《C8051F80x-83x》

72 13.3. Automatic Scanning.72 13.4. CS0 Comparator.73 13.5. CS0 Conversion Accumulator

74 13.6. Capacitive Sense Multiplexer

80 14. CIP-51 Microcontroller.82 14.1. Instruction Set.83 14.1.1. Instruction and CPU Timing

83 14.2. CIP-51 Register Descriptions

88 15. Memory Organization

92 15.1. Program Memory.93 15.1.1. MOVX Instruction and Program Memory

93 C8051F80x-83x

4 Rev. 1.0 15.2. Data Memory.93 15.2.1. Internal RAM

93 15.2.1.1. General Purpose Registers

94 15.2.1.2. Bit Addressable Locations

94 15.2.1.3. Stack

94 16. In-System Device Identification.95 17. Special Function Registers.97 18. Interrupts

102 18.1. MCU Interrupt Sources and Vectors.103 18.1.1. Interrupt Priorities.103 18.1.2. Interrupt Latency

103 18.2. Interrupt Register Descriptions.104 18.3. INT0 and INT1 External Interrupts.111 19. Flash Memory.113 19.1. Programming The Flash Memory.113 19.1.1. Flash Lock and Key Functions.113 19.1.2. Flash Erase Procedure

113 19.1.3. Flash Write Procedure

114 19.2. Non-volatile Data Storage

114 19.3. Security Options

114 19.4. Flash Write and Erase Guidelines.115 19.4.1. VDD Maintenance and the VDD Monitor

116 19.4.2. PSWE Maintenance.116 19.4.3. System Clock

117 20. Power Management Modes.120 20.1. Idle Mode.120 20.2. Stop Mode

121 20.3. Suspend Mode

121 21. Reset Sources.123 21.1. Power-On Reset.124 21.2. Power-Fail Reset / VDD Monitor

125 21.3. External Reset.126 21.4. Missing Clock Detector Reset

126 21.5. Comparator0 Reset

127 21.6. PCA Watchdog Timer Reset

127 21.7. Flash Error Reset

127 21.8. Software Reset.127 22. Oscillators and Clock Selection

129 22.1. System Clock Selection.129 22.2. Programmable Internal High-Frequency (H-F) Oscillator.131 22.3. External Oscillator Drive Circuit.133 22.3.1. External Crystal Example.135 22.3.2. External RC Example.136 22.3.3. External Capacitor Example.137 23. Port Input/Output

138 C8051F80x-83x Rev. 1.0

5 23.1. Port I/O Modes of Operation.139 23.1.1. Port Pins Configured for Analog I/O.139 23.1.2. Port Pins Configured For Digital I/O.139 23.1.3. Interfacing Port I/O to

5 V Logic.140 23.2. Assigning Port I/O Pins to Analog and Digital Functions.140 23.2.1. Assigning Port I/O Pins to Analog Functions

140 23.2.2. Assigning Port I/O Pins to Digital Functions.141 23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ...

142 23.3. Priority Crossbar Decoder

143 23.4. Port I/O Initialization

147 23.5. Port Match

150 23.6. Special Function Registers for Accessing and Configuring Port I/O

152 24. Cyclic Redundancy Check Unit (CRC0)159 24.1. 16-bit CRC Algorithm.160 24.2. 32-bit CRC Algorithm.161 24.3. Preparing for a CRC Calculation

162 24.4. Performing a CRC Calculation

162 24.5. Accessing the CRC0 Result

162 24.6. CRC0 Bit Reverse Feature.166 25. Enhanced Serial Peripheral Interface (SPI0)167 25.1. Signal Descriptions.168 25.1.1. Master Out, Slave In (MOSI)168 25.1.2. Master In, Slave Out (MISO)168 25.1.3. Serial Clock (SCK)168 25.1.4. Slave Select (NSS)168 25.2. SPI0 Master Mode Operation.168 25.3. SPI0 Slave Mode Operation.170 25.4. SPI0 Interrupt Sources

171 25.5. Serial Clock Phase and Polarity

171 25.6. SPI Special Function Registers.173 26. SMBus.180 26.1. Supporting Documents.181 26.2. SMBus Configuration.181 26.3. SMBus Operation

181 26.3.1. Transmitter Vs. Receiver.182 26.3.2. Arbitration.182 26.3.3. Clock Low Extension.182 26.3.4. SCL Low Timeout.182 26.3.5. SCL High (SMBus Free) Timeout

183 26.4. Using the SMBus.183 26.4.1. SMBus Configuration Register.183 26.4.2. SMB0CN Control Register