PDF《datasheet》

4 Banks ? Posted CAS ? Programmable CAS Latency: 3, 4, 5,

6 ? Programmable Additive Latency: 0,

1 ,

2 , 3,

4 ,

5 ? Write Latency(WL) = Read Latency(RL) -1 ? Burst Length:

4 , 8(Interleave/nibble sequential) ? Programmable Sequential / Interleave Burst Mode ? Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) ? Off-Chip Driver(OCD) Impedance Adjustment ? On Die Termination ? Special Function Support -50ohm ODT -High Temperature Self-Refresh rate enable ? Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C <

TCASE <

95 °C ? All of products are Lead-Free, Halogen-Free, and RoHS compliant The 256Mb DDR2 SDRAM is organized as a 4Mbit x

16 I/Os x

4 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1066Mb/sec/pin (DDR2-1066) for general applica- tions. The chip is designed to comply with the following key DDR2 SDRAM fea- tures such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of exter- nally supplied differential clocks. Inputs are latched at the crosspoint of dif- ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x16) device receive 13/9/2 addressing. The 256Mb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 256Mb DDR2 device is available in 84ball FBGAs(x16). NOTE : 1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in DDR2 SDRAM Device Operation &

Timing Dia- gram . 2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. -

5 - K4T56163QN datasheet DDR2 SDRAM Rev. 1.03 3. Package pinout/Mechanical Dimension &

Addressing 3.1 x16 Package Pinout (Top view) : 84ball FBGA Package NOTE : 1. VDDL and VSSDL are power and ground for the DLL. 2. In case of only

8 DQs out of

16 DQs are used, LDQS, LDQSB and DQ0~7 must be used. 3. A12 ball is only for MRS and EMRS mode setting. A B C D E F G H J K L VDD NC VSS DQ6 VSSQ LDM VDDQ VDDQ VDDQ VSSQ VSSQ LDQS LDQS DQ7 DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL VDD C........