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Q I&

Q Transmit Output Interface DDC0 2CDMA2000?1X or

1 UMTS DDC1 2CDMA2000?1X or

1 UMTS DDC10 2CDMA2000?1X or

1 UMTS DDC11 2CDMA2000?1X or

1 UMTS DUC11 2CDMA2000?1X or

1 UMTS DUC10 2CDMA2000?1X or

1 UMTS DUC1 2CDMA2000?1X or

1 UMTS DUC0 2CDMA2000?1X or

1 UMTS tdo tck trst_n tdi tms Transmit Output Data (to D/As) 1.2 Package/Ordering Information PRODUCT PACKAGE LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY GC5316 Thermally Enhanced Plastic BGA w/Heat Slug ?

388 ZED ?40°C to 85°C GC5316IZED GC5316IZED Tray,

40 GC5316 SLWS154A ? JANUARY

2004 ? REVISED MARCH

2004 www.ti.com

3 2 GC5316 Receive

16 16

16 16 Receive Input Data (to A/Ds) Receive Input Interface General purpose output sync Frame Sync DDC

10 &

11 Serial Outputs Receive Syncs rx_distribution Frame Sync DDC

0 &

1 DDC0 2CDMA2000?1X or

1 UMTS DDC1 2CDMA2000?1X or

1 UMTS DDC10 2CDMA2000?1X or

1 UMTS DDC11 2CDMA2000?1X or

1 UMTS rx_synca rx_syncb rx_syncc rx_syncd Receive input sync rxin_a rxin_b rxin_c rxin_d addcclk rxout_0_a rxout_0_b rxout_0_c rxout_0_d rxout_1_a rxout_1_b rxout_1_c rxout_1_d rx_sync_out_0 rxout_10_a rxout_10_b rxout_10_c rxout_10_d rxout_11_a rxout_11_b rxout_11_c rxout_11_d rx_sync_out_5 rx_sync_out I CDMA Ch A I CDMA Ch B Q CDMA Ch A Q CDMA Ch B For CDMA For UMTS Imsb UMTS Imsb?1 UMTS Qmsb UMTS Qmsb?1 UMTS rxclk (receive chip clock) DDCs

2 through

9 Figure 1. Receive Section The receive section of the GC5316 consists of the receive input interface, the rx_distribution bus, and

12 digital downconverter blocks. The purpose of the receive input interface is to accept signal data from four input ports (generally from analog-to-digital converters) and to distribute the data to the DDC blocks. The input interface also has a user-controlled test generator and noise source, as well as a resampling block. The resampler accepts real inputs at 3/4rxclk or rxclk rate, mixes down by Fs/4, low-pass filters, and decimates to rxclk/2. This is useful for handling data at 3/4 rxclk rate (for example, a 92.16-MSPS adcclk rate with a 122.88-MHz rxclk). It is also useful to process more than

12 CDMA signals when sampling at rxclk rate. The rx_distribution bus distributes the four channels of signal data to each of the

12 DDC blocks. Each DDC block selects one of the four channels from the rx_distribution bus and then performs downconversion tuning, programmable delay, channel filtering with decimation, power measurement, fixed gain adjust, and automatic gain control. Each DDC block can support one UMTS channel or two CDMA channels. An optional mode permits stacking two DDC blocks to provide double-length channel filtering. Tuned, filtered, and decimated signal data is output in bit serial format. GC5316 SLWS154A ? JANUARY

2004 ? REVISED MARCH

2004 www.ti.com

4 2.1 Receive Input Interface FIFO R esampler Block Select Select FIFO Bypass Bypass

18 18

18 18 Upper

16 of

18 Upper

16 of

18 16 Test &

Noise Generator Test &

Noise Generator

16 16 Resampler Block Select Select FIFO FIFO Bypass Bypass

18 18

18 18 Upper16 of

18 Upper

16 of

18 16

16 16 Test &

Noise Generator Test &

Noise Generator

16 I Q I Q bus

0 bus

1 bus

2 bus

3 rxin_a rxin_b rxin_c rxin_d Select resampler_ena Special 92.16 MSPS input rate mode rx_distribution Figure 2. Receive Input Interface The four ports support four independent real input signals or two complex. Complex signal data is input with I data driving one input port and Q data driving another. This means that there are only two signal data ports available when in complex input mode. The mapping of I and Q data onto the four input ports is programmable. 2.1.1 Test and Noise Generator and FIFO Incoming data first enters the test and noise generator block. This block can either pass the data through, replace the input data with a pattern generated internally (useful in test), or can add noise to the input at a user programmable level. Most appli........