PDF《TMS320F28xx and TMS320F28xxx DSP》

Reference Design SLVA296ACFebruary 2008CRevised April

2008 TMS320F28xx and TMS320F28xxx DSP Power Reference Design This reference design takes into account the voltage, current, and start-up requirements of the TMS320F280x Digital Signal Processor (DSP) families.

The operating input voltage ranges from 3.4 V to

6 V. This design is a high-efficiency solution that provides two voltage rails (1.8-V core supply and 3.3-V I/O supply) and an active-low reset signal to the DSP. This design can be easily adapted to fit requirements for the TMS320F28xxx and TMS320F281x, which have a 1.9-V core supply and 3.3-V I/O supply. Features ? Provides core and I/O voltages from 3.4-V to 6-V input voltages ? High-efficiency solution ? Small solution size using dual converter ? Optional power-save mode, watchdog timer, and power-fail comparator Related Documentation For detailed information about operating conditions and component characteristics, click links in Table 1: Table 1. Related Documentation Links DEVICE DATA SHEET TMS320F28xxx TMS320F28335, F28334, F28332 F28235, F28234, F28232 DSCs (SPRS439) TMS320F281x TMS320F2810, F2811, F2812, C2810, C2811, C2812 DSPs (SPRS174) TMS320F280x TMS320F2809, F2808, F2806, F2802, F2801, C2802, C2801, F2801x DSPs (SPRS230) TPS62400 Adjustable Dual Step-Down Converter (SLVS681) TPS62402 TPS62402 Dual Step-Down Converter (SLVS681) TPS3306-18 Dual Processor Supervisor (SLVS290) Requirements The TMS320F280x requires two input rails: 1.8 V for the core and 3.3 V for input/output (I/O). To avoid glitches on power up, the 1.8-V rail must be powered prior to or simultaneously with the 3.3-V rail, ensuring that the 1.8-V rail reaches 0.7 V before the 3.3-V rail reaches 0.7 V. See the Power Sequencing section of the relevant DSP data sheet for further details. SLVA296ACFebruary 2008CRevised April

2008 TMS320F28xx and TMS320F28xxx DSP Power Reference Design

1 Submit Documentation Feedback Implementation www.ti.com Implementation This design uses the TPS62402 dual-output, step-down converter and the TPS3306-18 dual-supply voltage supervisor (SVS) as shown in Figure 1. Figure 1. Block Diagram of Power Design Start-Up The TPS62402 is a dual step-down converter, with an enable (EN) pin for each output. In this design, the EN1 pin is connected to the input voltage (VIN), so that the 1.8-V rail voltage rises first. The EN2 pin is connected to the 1.8-V rail. Once the voltage reaches the enable threshold of 1.2 V, the 3.3-V rail voltage rises. The 1.8-V rail voltage rises before the 3.3-V rail, so that the start-up requirements are met. Figure

2 and Figure

3 show the start-up waveforms using a VIN of

5 V and a standard Spectrum Digital EVM board for the F2808 (part number 761132) as the load. The power chip on the board and related circuitry (output capacitors, feedback resistors) are removed, and this design is used to power the board. The TPS62401EVM-167 (HPA167-002) board with the TPS62402DRC instead of the TPS62401DRC is connected to the TPS3305-18D SVS. Then, the voltage rails and reset signal are attached to the F2808 EVM. The TPS62402 is set to forced-PWM mode.

2 TMS320F28xx and TMS320F28xxx DSP Power Reference Design SLVA296ACFebruary 2008CRevised April

2008 Submit Documentation Feedback www.ti.com Start-Up Figure 2. The 1.8-V Rail Voltage Rises Before the 3.3-V Rail SLVA296ACFebruary 2008CRevised April

2008 TMS320F28xx and TMS320F28xxx DSP Power Reference Design

3 Submit Documentation Feedback Voltage Ripple www.ti.com Figure 3. The RESET Signal Held Low for a 100-ms Typical Fixed Delay Voltage Ripple For precise measurements on the analog-to-digital converter (ADC) of the DSP, power supply noise and ripple needs to be low. The peak-to-peak voltage ripple values of this design at a Vin of