PDF《ADP5310》

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28 TABLE OF CONTENTS Features

1 Applications.1 Typical Application Circuit

1 General Description.1 Revision History

2 Detailed Functional Block Diagram

3 Specifications.4 Buck Regulators and Load Switch Specifications.5 Absolute Maximum Ratings.7 Thermal Resistance.7 ESD Caution.7 Pin Configuration and Function Descriptions.8 Typical Performance Characteristics

9 Theory of Operation

18 Buck Regulator Operation Modes.18 Adjustable and Fixed Output Voltages

19 Undervoltage Lockout (UVLO)19 Enable and Shutdown Features.19 Internal Linear Regulator (VREG)19 Oscillator and Synchronization.19 Current Limit.19 Short-Circuit Protection.19 Soft Start

19 Startup with Precharged Output

19 100% Duty Operation.19 Active Discharge.20 Power-Good Function.20 Load Switch.20 Thermal Shutdown

20 Applications Information.21 External Component Selection

21 Selecting the Inductor.21 Output Capacitor.21 Input Capacitor.21 Adjustable Output Voltage Programming

22 Efficiency.22 Recommended Buck External Components

22 Capacitor Selection

24 Circuit Board Layout Recommendations

24 Typical Application Circuits.25 Factory Programmable Options.26 Outline Dimensions.28 Ordering Guide

28 REVISION HISTORY 11/2016―Rev.

0 to Rev. A Changes to Ordering Guide

28 4/2015―Revision 0: Initial Version Moved Circuit Board Layout Recommendations Section and Figure 57.24 Data Sheet ADP5310 Rev. A | Page

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28 DETAILED FUNCTIONAL BLOCK DIAGRAM VREG SYNC/MODE 1.2V LDO 2.55V 2.4V UVLO PVIN2 PVIN1 BAND GAP BIAS AND CONTROL LOGIC S/H OSC 1.2V 0.4V CH1 CH2 1.2MHz OSC CH1 CH2 CH2 SYNC P_ILIMIT 1.2A IMIN N_ILIMIT PWM 0.808V 0.8V PSM SW1 FB1 PVIN1 CONTROL LOGIC DRIVER VIN DRIVER VIN C0.5A (PWM) 0A (PSM) RDS(ON) * kr VIN 300mA/kr RDS(ON) * kr VIN EN1 0.4V SOFT START 0.8V V TO I PWRGD 0.736V 0.696V FB1 CHANNEL

1 PGND1 P_ILIMIT 0.6A IMIN N_ILIMIT PWM 0.808V 0.8V PSM SW2 FB2 VOUT3 PVIN2 CONTROL LOGIC DRIVER VIN DRIVER VIN C0.5A (PWM) 0A (PSM) RDS(ON) * kr VIN 300mA/kr RDS(ON) * kr VIN SOFT START 0.8V V TO I CHANNEL

2 CHANNEL

3 PGND2 EN3 1.2V 0.4V DRIVER ADP5310 13008-002 1.2V SLOPE COMPENSATION SLOPE COMPENSATION Figure 2. ADP5310 Data Sheet Rev. A | Page

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28 SPECIFICATIONS VIN =

6 V, VREG = 3.9 V, TJ = ?40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VIN 2.7 15.0 V PVIN1 and PVIN2 pins QUIESCENT CURRENT PVIN1 and PVIN2 pins Operating Quiescent Current Standby Operation IQ1

700 1850 nA ?40°C ≤TJ ≤ +85°C, EN1 = SYNC/MODE = low

700 3800 nA ?40°C ≤TJ ≤ +125°C, EN1 = SYNC/MODE = low PWM Operation IQ3 1.4 1.65 mA EN1 = SYNC/MODE = high UNDERVOLTAGE LOCKOUT UVLO PVIN2 pin UVLO Threshold Rising VUVLO_RISING 2.55 2.75 V Falling VUVLO_FALLING 2.15 2.40 V Hysteresis VHYS

150 mV OSCILLATOR CIRCUIT For Channel

1 and Channel 2, PWM mode Switching Frequency fSW

1050 1200

1350 kHz

525 600

675 kHz Feedback (FB) Threshold of Frequency Fold VOSC_FOLD 0.3 V SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNCCLOCK

400 800 kHz fSW =

600 kHz SYNCCLOCK

800 1400 kHz fSW = 1.2 MHz SYNC High Level Threshold SYNCHIGH 1.2 V SYNC Low Level Threshold SYNCLOW 0.4 V SYNC Pulse On Time Range SYNCON

80 1/fSW ?

150 ns EN1 and EN3 Input High Level Threshold VIH 1.2 V Input Low Level Threshold VIL 0.4 V Input Leakage Current ILEAKAGE

300 nA INTERNAL POWER GOOD Internal Power-GoodThreshold VPWRGD(RISE)

88 92

96 % Internal Power-Good Hysteresis VPWRGD(HYS)