PDF《TEA1755T》

494 mV. At initial start-up, switching is prevented until the capacitor on the LATCH pin is charged above

582 mV. No internal filtering is performed on this pin. An internal 1.75 V clamp protects the pin from excessive voltages. 7.1.5 Fast latch reset In a typical application, the mains can be interrupted briefly to reset the latched protection. The bulk capacitor Cbulk does not have to discharge for this latched protection to reset. When the VINSENSE voltage drops below

750 mV and is then raised to

860 mV, the latched protection is reset. The latched protection is also reset by removing both the voltage on the VCC and HV pins. 7.1.6 Overtemperature protection An accurate internal temperature protection is provided in the IC. When the junction temperature exceeds the thermal shut-down temperature, the IC stops switching. While OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC supply voltage is not sufficient, the OTP circuit is supplied from the HV pin. OTP is a latched protection. It is reset by removing the voltage from both the VCC and HV pins or by the fast latch reset function (see Section 7.1.5). 7.2 Power factor correction circuit The Power Factor Correction (PFC) circuit operates in Quasi-Resonant (QR) or Discontinuous Conduction Mode (DCM) with valley switching. The next primary stroke is only started when the previous secondary stroke has ended and the voltage across the PFC MOSFET has reached the minimum value. VPFCAUX is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch. 7.2.1 ton control (PFCCOMP pin) The power factor correction circuit is operated in ton control. The resulting mains harmonic reduction is well within the class-D requirements. VPFCCOMP determines the on-time of the PFC. The VVOSENSE is the transconductance amplifier input which outputs current to the PFCCOMP pin. The regulati........