编辑: ddzhikoi 2019-07-16
1 Traffic-Light Controller

1 Traffic Light Controller Ya Ga Ra Gb Yb Rb Sa Sb Clock Street a Street b Street a is the main street and street b is the side street Sa=1, vehicle approaching on street a.

Sb=1, vehicle approaching on street b. Light on a stays green until vehicle on b. Then light on b changes green and changes back after

50 seconds. If another car on b, then light on b remains green for

10 more seconds. When a is green remains green for at least

60 seconds. Finite state Moore machine for traffic light controller

2 S0 GaRb S1 GaRb S2 GaRb S3 GaRb S4 GaRb S5 GaRb S6 YaRb S12 RaYb S11 RaGb S10 RaGb S9 RaGb S8 RaGb S7 RaGb (Sa + Sb') Sa'Sb Sb' Sb Clock cycle period is

10 seconds Sa=1, vehicle approaching on street a Sb=1, vehicle approaching on street b

2 VHDL Model for Traffic-Light Controller entity traffic_light is port (clk, Sa , Sb: in bit;

Ra, Rb, Ga, Ya, Yb: inout bit);

end traffic_light;

architecture behave of traffic_light is signal state, nextstate: integer range

0 to 12;

type light is (R,Y, G);

signal lightA, lightB: light;

begin process(state, Sa, Sb) begin Ra

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