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TMS320C6748 www.

ti.com SPRS590DCJUNE 2009CREVISED OCTOBER

2011 TMS320C6748 Fixed/Floating-Point DSP Check for Samples: TMS320C6748

1 TMS320C6748 Fixed/Floating-Point DSP 1.1 Features

12 ? Highlights ? TMS320C674x Floating-Point VLIW DSP Core C 375/456-MHz C674x Fixed/Floating-Point C Load-Store Architecture With Non-Aligned VLIW DSP Support C Supports TI'

s Basic Secure Boot C

64 General-Purpose Registers (32 Bit) C Enhanced Direct-Memory-Access Controller C Six ALU (32-/40-Bit) Functional Units (EDMA3) ? Supports 32-Bit Integer, SP (IEEE Single C Serial ATA (SATA) Controller Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point C DDR2/Mobile DDR Memory Controller ? Supports up to Four SP Additions Per C Two Multimedia Card (MMC)/Secure Digital Clock, Four DP Additions Every

2 Clocks (SD) Card Interface ? Supports up to Two Floating Point (SP or C LCD Controller DP) Reciprocal Approximation (RCPxP) C Video Port Interface (VPIF) and Square-Root Reciprocal C 10/100 Mb/s Ethernet MAC (EMAC) Approximation (RSQRxP) Operations Per C Programmable Real-Time Unit Subsystem Cycle C Three Configurable UART Modules C Two Multiply Functional Units C USB 1.1 OHCI (Host) With Integrated PHY ? Mixed-Precision IEEE Floating Point C USB 2.0 OTG Port With Integrated PHY Multiply Supported up to: C One Multichannel Audio Serial Port C

2 SP x SP → SP Per Clock C Two Multichannel Buffered Serial Ports C

2 SP x SP → DP Every Two Clocks ? 375/456-MHz C674x Fixed/Floating-Point VLIW C

2 SP x DP → DP Every Three Clocks DSP C

2 DP x DP → DP Every Four Clocks ? C674x? Instruction Set Features ? Fixed Point Multiply Supports Two

32 x C Superset of the C67x+? and C64x+? ISAs 32-Bit Multiplies, Four

16 x 16-Bit C Up to 3648/2746 C674x MIPS/MFLOPS Multiplies, or Eight

8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples C Byte-Addressable (8-/16-/32-/64-Bit Data) C Instruction Packing Reduces Code Size C 8-Bit Overflow Protection C All Instructions Conditional C Bit-Field Extract, Set, Clear C Hardware Support for Modulo Loop C Normalization, Saturation, Bit-Counting Operation C Compact 16-Bit Instructions C Protected Mode Operation ? C674x Two Level Cache Memory Architecture C Exceptions Support for Error Detection and C 32K-Byte L1P Program RAM/Cache Program Redirection C 32K-Byte L1D Data RAM/Cache ? Software Support C 256K-Byte L2 Unified Mapped RAM/Cache C TI DSP/BIOS? C Flexible RAM/Cache Partition (L1 and L2) C Chip Support Library and DSP Library ? Enhanced Direct-Memory-Access Controller

3 ? 128K-Byte RAM Memory (EDMA3): ? 1.8V or 3.3V LVCMOS IOs (except for USB and C

2 Channel Controllers DDR2 interfaces) C

3 Transfer Controllers ? Two External Memory Interfaces: C

64 Independent DMA Channels C EMIFA C

16 Quick DMA Channels ? NOR (8-/16-Bit-Wide Data) C Programmable Transfer Burst Size ? NAND (8-/16-Bit-Wide Data)

1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright ? 2009C2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C6748 SPRS590DCJUNE 2009CREVISED OCTOBER

2011 www.ti.com ? 16-Bit SDRAM With

128 MB Address C Supports TDM, I2S, and Similar Formats Space C AC97 Audio Codec Interface C DDR2/Mobile DDR Memory Controller C Telecom Interfaces (ST-Bus, H100) ? 16-Bit DDR2 SDRAM With

512 MB C 128-channel TDM Address Space or C FIFO buffers for Transmit and Receive ? 16-Bit mDDR SDRAM With

256 MB ? 10/100 Mb/s Ethernet MAC (EMAC): Address Space C IEEE 802.3 Compliant ? Three Configurable

16550 type UART Modules: C MII Media Independent Interface C With Modem Control Signals C RMII Reduced Media Independent Interface C 16-byte FIFO C Management Data I/O (MDIO) Module C 16x or 13x Oversampling Option ? Video Port Interface (VPIF): ? LCD Controller C Two 8-bit SD (BT.656), Single 16-bit or Single ? Two Serial Peripheral Interfaces (SPI) Each Raw (8-/10-/12-bit) Video Capture Channels With Multiple Chip-Selects C Two 8-bit SD (BT.656), Single 16-bit Video ? Two Multimedia Card (MMC)/Secure Digital (SD) Display Channels Card Interface with Secure Data I/O (SDIO) ? Universal Parallel Port (uPP): Interfaces C High-Speed Parallel Interface to FPGAs and ? Two Master/Slave Inter-Integrated Circuit (I2 C Data Converters Bus?) C Data Width on Each of Two Channels is 8- to ? One Host-Port Interface (HPI) With 16-Bit-Wide 16-bit Inclusive Muxed Address/Data Bus For High Bandwidth C Single Data Rate or Dual Data Rate Transfers ? Programmable Real-Time Unit Subsystem C Supports Multiple Interfaces with START, (PRUSS) ENABLE and WAIT Controls C Two Independent Programmable Realtime ? Serial ATA (SATA) Controller: Unit (PRU) Cores C Supports SATA I (1.5 Gbps) and SATA II (3.0 ? 32-Bit Load/Store RISC architecture Gbps) ? 4K Byte instruction RAM per core C Supports all SATA Power Management ?

512 Bytes data RAM per core Features ? PRU Subsystem (PRUSS) can be disabled C ........