PDF《2 Gbit, 3V Page Mode》

S70GL02GP

2 Gbit, 3V Page Mode S70GL-P MirrorBit? Flash Cypress Semiconductor Corporation ?

198 Champion Court ? San Jose, CA 95134-1709 ? 408-943-2600 Document Number: 002-01338 Rev.

*E Revised November 09,

2017 General Description The Cypress S70GL02GP

2 Gbit Mirrorbit Flash device is fabricated on 90-nm process technology. This device offers a fast page access time of

25 ns with a corresponding random access time of

110 ns. It features a Write Buffer that allows a maximum of

32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard single byte/word programming algorithms. This makes the device an ideal product for today'

s embedded applications that require higher density, better performance and lower power consumption. This document contains information for the S70GL02GP device, which is a dual die stack of two S29GL01GP die. For detailed specifications, refer to the discrete die datasheet provided in Table 1. Distinctive Characteristics ? Two

1024 Mbit (S29GL01GP) in a single 64-ball Fortified- BGA package (see S29GL01P datasheet for full specifications) ? Single 3V read/program/erase (3.0V - 3.6V) ?

90 nm MirrorBit process technology ? 8-word/16-byte page read buffer ? 32-word/64-byte write buffer reduces overall programming time for multiple-word writes ? Secured Silicon Sector region C 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number C Can be programmed and locked at the factory or by the customer ? Uniform 64Kword/128KByte Sector Architecture C S70GL02GP: two thousand forty-eight sectors ? 100,000 erase cycles per sector typical ? 20-year data retention typical ? Offered Packages C 64-ball Fortified BGA ? Suspend and Resume commands for Program and Erase operations ? Write operation status bits indicate program and erase operation completion ? Unlock Bypass Program command to reduce programming time ? Support for Common Flash Interface (CFI) ? Persistent and Password methods of Advanced Sector Protection ? WP#/ACC input C Accelerates programming time (when VACC is applied) for greater throughput during system production C Protects first or last sector of each die, regardless of sector protection settings ? Hardware reset input (RESET#) resets device ? Ready/Busy# output (RY/BY#) detects program or erase cycle completion Table 1. Affected Documents/Related Documents Title Publication Number S29GL01GP, S29GL512P, S29GL256P, S29GL128P

1 Gbit, 512, 256,

128 Mbit,

3 V, Page Flash with

90 nm MirrorBit Process Technology 002-00886 Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP Performance Characteristics Notes 1. Access times are dependent on VCC and VIO operating ranges. See Ordering Information on page

4 for further details. 2. Contact a sales representative for availability. Max. Read Access Times (ns)(Note 1) Parameter

2 Gb Random Access Time (tACC)

110 Page Access Time (tPACC)

25 CE# Access Time (tCE)

110 OE# Access Time (tOE)

25 Current Consumption (typical values) Random Access Read

30 mA 8-Word Page Read

1 mA Program/Erase

50 mA Standby

2 ?A Program &

Erase Times (typical values) Single Word Programming

60 ?s Effective Write Buffer Programming (VCC) Per Word

15 ?s Effective Write Buffer Programming (VACC) Per Word

15 ?s Sector Erase Time (64 Kword Sector) 0.5 s Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP Contents 1. Ordering Information.4 1.1 Recommended Combinations.4 2. Input/Output Description and Logic Symbol.5 2.1 Special Handling Instructions for BGA Package.6 2.2 LSE064―64 ball Fortified Ball Grid Array,

13 ?

11 mm .

7 3. Memory Map.8 4. Autoselect

8 5. Erase And Programming Performance.8 6. BGA Package Capacitance

9 7. Revision History.10 Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP 1. Ordering Information The ordering part number is formed by a valid combination of the following: 1.1 Recommended Combinations Recommended Combinations table below list various configurations planned to be available in volume. The table below will be updated as new combinations are released. Check with your local sales representative to confirm availability of specific configuration not listed or to check on newly released combinations. Notes 1. Contact a local sales representative for availability. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. 3. Packing Type

0 is standard option. S70GL02GP

11 F F C R1

0 PACKING TYPE

0 = Tray (standard;

see (Note 3)

2 =

7 Tape and Reel

3 =

13 Tape and Reel MODEL NUMBER (VIO range, protection when WP# =VIL) R1 = VIO = VCC = 3.0 to 3.6V, highest address sector protected R2 = VIO = VCC = 3.0 to 3.6V, lowest address sector protected TEMPERATURE RANGE I = Industrial (C40 °C to +85 °C) C = Commercial (0 °C to +85 °C) PACKAGE MATERIALS SET A = Pb (Note 1) F = Pb-free PACKAGE TYPE F = Fortified Ball Grid Array, 1.0 mm pitch package SPEED OPTION

11 =

110 ns DEVICE NUMBER/DESCRIPTION S70GL02GP 3.0V-only,

2048 Megabit (128 M x 16-Bit/256 M x 8-Bit) Page-Mode Flash Memory Manufactured on

90 nm MirrorBit process technology S29GL-P Recommended Combinations (Note 1) Base OPN Speed (ns) Package and Temperature Model Number Packing Type Ordering Part Number (x = Packing Type) S70GL02GP

110 FFC, FAC (Note 2) R1, R2 0, 2,

3 (Note 3) S70GL02GP11FFCR1x S70GL02GP11FFCR2x S70GL02GP11FACR1x S70GL02GP11FACR2x Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP 2. Input/Output Description and Logic Symbol Table

1 identifies the input and output package connections provided on the device. Table 1. Input/Output Description Symbol Type Description A26CA0 Input Address lines for GL02GP DQ14CDQ0 I/O Data input/output. DQ15/A-1 I/O DQ15: Data input/output in word mode. A-1: LSB address input in byte mode. CE# Input Chip Enable. OE# Input Output Enable. WE# Input Write Enable. VCC Supply Device Power Supply. VIO Supply Versatile IO Input. VSS Supply Ground. RY/BY# Output Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively erasing or programming. At High Z, the device is in ready. BYTE# Input Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-DQ7 are active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active. RESET# Input Hardware Reset. Low = device resets and returns to reading array data. WP#/ACC Input Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost sectors. At VHH, accelerates programming;

automatically places device in unlock bypass mode. Should be at VIH for all other conditions. NC No Connect Not connected internally. Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP 2.1 Special Handling Instructions for BGA Package Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Figure 2.1 64-ball Fortified Ball Grid Array 64-ball Fortified BGA Top View, Balls Facing Down A2 C2 D2 E2 F2 G2 H2 A3 C3 D3 E3 F3 G3 H3 A4 C4 D4 E4 F4 G4 H4 A5 C5 D5 E5 F5 G5 H5 A6 C6 D6 E6 F6 G6 H6 A7 C7 D7 E7 F7 G7 H7 DQ15/A-1 VSS BYTE# A16 A15 A14 A12 A13 DQ13 DQ6 DQ14 DQ7 A11 A10 A8 A9 VCC DQ4 DQ12 DQ5 A19 A21 RESET# WE# DQ11 DQ3 DQ10 DQ2 A20 A18 WP#/ACC RY/BY# DQ9 DQ1 DQ8 DQ0 A5 A6 A17 A7 OE# VSS CE# A0 A1 A2 A4 A3 A1 C1 D1 E1 F1 G1 H1 NC NC VIO NC NC NC A26 NC A8 C8 B2 B3 B4 B5 B6 B7 B1 B8 D8 E8 F8 G8 H8 A25 NC A24 VSS VIO A23 A22 NC Document Number: 002-01338 Rev. *E Page

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11 S70GL02GP 2.2 LSE064―64 ball Fortified Ball Grid Array,

13 ?

11 mm Figure 2.2 LSE064―64-ball Fortified Ball Grid Array (FBGA),

13 x

11 mm

3611 16-038.15 11.13.6 PACKAGE LSE

064 JEDEC N/A D x E 13.00 mm x 11.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE A1 0.40 --- --- BALL HEIGHT A2 0.79 --- 0.91 BODY THICKNESS D 13.00 BSC. BODY SIZE E 11.00 BSC. BODY SIZE D1 7.00 BSC. MATRIX FOOTPRINT E1 7.00 BSC. MATRIX FOOTPRINT MD

8 MATRIX SIZE D DIRECTION ME

8 MATRIX SIZE E DIRECTION n

64 BALL COUNT ?b 0.50 0.60 0.70 BALL DIAMETER eE 1.00 BSC. BALL PITCH eD 1.00 BSC BALL PITCH SD / SE 0.50 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL MD IS THE BALL MATRIX SIZE IN THE D DIRECTION. SYMBOL ME IS THE BALL MATRIX SIZE IN THE E DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR........