PDF《液晶显示模块使用手册》

0 --- ns tCE2 VCE data off time

0 Note: 1. tCYR = 3tC 2. t ACV = 3t C C120 3. t CEA = 2t C C120 z Display memory WRITE timing Signal Symbol Parameter Rating Unit Condition min max EXT ?0 tC Clock cycle

100 --- ns VCE tW VCE high level pulse width tc-40 --- ns tCE VCE low level pulse width 2tc-40 --- ns tCYR Read cycle time 3tc --- ns tAHC VCE address hold time (fall) 2tc-40 --- ns CL = 100pF VA0 tASC VCE address setup time (fall) tc-55 --- ns +1TTL to VA15 tCA VCE address hold time (rise)

5 --- ns tAS VR/W address setup time (fall)

0 --- ns tAH2 VR/W address hold time (rise)

15 --- ns VR/W tWSC VCE write setup time (fall) tc-55 --- ns tWHC VCE write hold time (fall) tc/2-40 --- ns VD0 tDSC VCE data input setup time (fall) twsc-10 --- ns to VD7 tDHC VCE data input hold time (fall) 2tc-30 --- ns tDH2 VR/W data hold time (rise) 10*

50 ns * Lines VD0 to VD7 are latched. EXTφO VCE VA0?VA15 VR/W VD0?VD7 tACY tCEA tAHC tCYR tCE tW tRCH tCE3 tOH2 tAS tW tC tRCS EXTφO VA0?VA15 VCE VD0?VD7 VR/W tC tW tCE tAS tAHC tCYW tWHC tOHC tOH2 tAH2 tCA tOHS tWSC tAS LCD MODULE WS320240C Version:1.0 Fep-15-2007

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32 z LCD control timing Signal Symbol Parameter Rating Unit Condition min max EXT ?0 tC Clock cycle

100 --- ns tr VCE high level pulse width ---

35 ns tf VCE low level pulse width ---

35 ns XSCL tCX Shift clock cycle time 4tc --- ns tWX XSCL clock pulse width tcx2-80 --- ns XD0 tDH X-data hold time tcx2-100 --- ns to XD3 tDS X-data setup time tcx2-100 --- ns VDD=5.0V LP tLS Latch data setup time tcx2-100 --- ns ±10% tWL LP signal pulse width tcx4-80 --- ns CL=150F tL1 XECL setup time tc-30 --- ns tL2 XECL data hold time tc-30 --- ns XSCL tS1 Enable setup time tc-30 --- ns tS1 Enable delay time tc-30 --- ns tWXE XECL clock pulse width tcx3-80 --- ns WF tDF Time allowance of WF delay ---

100 ns YSCL tLD LP delay time against YSCL tcx4-100 --- ns tWY YSCL clock pulse width tcx4-80 --- ns YD tDHY Y-data hold time tcx6-100 --- ns ROW NO LP YD ........