PDF《TEST REPORT》

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2018 TR058 Rev.0.00 Jan 5,

2018 HS-26C32EH Total Dose Test TEST REPORT Introduction This report describes the results of Low Dose Rate (LDR) total dose testing of the HS-26C32EH quad differential line receiver. The data originated from routine production wafer-by-wafer acceptance testing of the part. Two versions of the HS-26C32 are available. The base HS-26C32RH is acceptance tested on a wafer-by-wafer basis to 300krad(Si) at High Dose Rate (HDR), as defined in MIL-STD-883 test method

1019 (50C300rad(Si)/s). The HS-26C32EH is acceptance tested on a wafer-by-wafer basis to 300krad(Si) at HDR and to 50krad(Si) at LDR, also as defined in MIL-STD-883 test method

1019 (0.01rad(Si)/s maximum). The HS-26C32RH and HS-26C32EH are identical parts and differ only in radiation lot acceptance testing (RLAT) procedures. Product Description The HS-26C32RH and HS-26C32EH are differential line receivers designed for digital data transmission over balanced lines and meet the requirements of EIA Standard RS-422. Radiation hardened CMOS processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. The HS-26C32RH and HS- 26C32EH have a typical input sensitivity of 200mV over the common-mode input voltage range of ±7V. The receivers are also equipped with input fail safe circuitry, which causes the outputs to go to logic

1 when the inputs are open. Enable and Disable functions are common to all four receivers. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency, Land and Maritime (DLA). The SMD number listed in this report must be used when ordering. Detailed electrical specifications for these devices are contained in SMD 5962-95689. Related Literature ? MIL-STD-883G test method 1019.7 ? For a full list of related documents, visit our website ? HS-26C32EH product page Figure 1. HS-26C32EH Block Diagram ENABLE ENABLE AOUT BOUT COUT DIN DOUT DIN CIN CIN BIN BIN AIN AIN + - + - + - + - TR058 Rev.0.00 Page

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2018 HS-26C32EH Total Dose Test 1. Test Description 1.1 Irradiation Facilities All data was derived from wafer acceptance testing results. LDR irradiation was performed at 0.010rad(Si)/s per MIL-STD-883 Method 1019.7, using the Intersil N40 panoramic irradiator. 1.2 Test Fixturing Figure

2 shows the configuration used for biased irradiation in conformance with Standard Microcircuit Drawing (SMD) 5962-95689. Notes: 1. VDD = +5V ±5% 2. GND = ground 3. All resistors are 47kΩ ± 5% 4. Use generic 16-pin universal board 5. Use patch labeled HS26C32 Figure 2. Irradiation Bias Configuration *1'

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2018 HS-26C32EH Total Dose Test 1.3 Characterization Equipment and Procedures All electrical testing was performed at room temperature using the production Automated Test Equipment (ATE), with datalogging at each downpoint. 1.4 Experimental Matrix The experimental matrix consisted of

16 samples irradiated at LDR with all pins grounded and

16 samples irradiated at LDR under bias. All samples were part of the wafer-by-wafer acceptance testing procedure. Samples of the HS-26C32EH die were drawn from production lot G2A0PEH and were packaged in the standard hermetic 16-Ld flatpack (CDFP4-F16) production package. Samples were processed through the standard burn-in cycle before irradiation and were screened to the SMD limits at room, low, and high temperatures before the test. TR058 Rev.0.00 Page

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