PDF《STM32F303xB/C Errata sheet》

July

2016 DocID023637 Rev

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1 STM32F303xB/C Errata sheet STM32F303xB/C Rev Z and Y device limitations Silicon identification This errata sheet applies to revisions Z and Y of the STMicroelectronics STM32F303xB/C products.

This family features an ARM? 32-bit Cortex? -M4 with FPU, for which an errata notice is also available (see Section

1 for details). Section

2 gives a detailed description of the product silicon limitations. The products are identifiable as shown in Table 1: ? By the revision code marked below the order code on the device package ? By the last three digits of the internal order code printed on the box label The full list of part numbers is shown in Table 2. Table 1. Device identification(1) 1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the STM32F3xx reference manual for details on how to find the revision code). Order code Revision code(2) marked on device 2. Refer to the device datasheet for details on how to identify the revision code on the different packages. STM32F303xB/C Z and Y Table 2. Device summary Reference Part number STM32F303xB/C STM32F303CB, STM32F303RB, STM32F303VB, STM32F303CC, STM32F303RC, STM32F303VC www.st.com Contents STM32F303xB/C 2/25 DocID023637 Rev

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1 ARM? 32-bit Cortex?-M4 with FPU limitations

5 1.1 Cortex?-M4 with FPU interrupted loads to stack pointer can cause erroneous behavior

5 1.2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used

6 2 STM32F303xB/C silicon limitations

7 2.1 System limitations

9 2.1.1 SYSCFG_CFGR2, comparators and operational amplifiers control registers reset by APB2 reset

9 2.1.2 Data Read when the CPU accesses successively SRAM address A and SRAM address A + offset of

16 KBytes (0x4000)9 2.1.3 Wakeup sequence from Standby mode when using more than one wakeup source

9 2.1.4 Full JTAG configuration without NJTRST pin cannot be used

10 2.1.5 CCM RAM write protection register SYSCFG_RCR not reset by system reset

10 2.2 ADC limitations

11 2.2.1 DMA Overrun in dual interleaved mode with single DMA channel . . . .

11 2.2.2 Sampling time shortened in JAUTO autodelayed mode

11 2.2.3 Injected queue of context is not available in case of JQM =

0 11 2.2.4 Load multiple not supported by ADC interface

11 2.2.5 ADEN bit cannot be set immediately after the ADC calibration is done .

12 2.2.6 Overrun flag might not be set when the converted data have not been read before new data are written

12 2.2.7 ADC differential mode common mode input range

12 2.2.8 Imprecise VREFINT calibration values

12 2.3 SPI peripheral limitations

13 2.3.1 Packing mode limitation at reception

13 2.3.2 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer '

-1'

14 2.3.3 BSY bit may stay high at the end of a SPI data transfer in slave mode .

14 2.3.4 Last data bit or CRC calculation may be corrupted for the data received in SPI/I2S master mode depending on the feedback communication clock timing with respect to the APB clock

15 2.4 I2 C peripheral limitations

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3 2.4.1 10-bit slave mode: wrong direction bit value after Read header reception

15 2.4.2 10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong slave address detection

16 2.4.3 Wakeup frames may not wakeup the MCU mode when STOP mode entry follows I2 C enabling

17 2.4.4 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2C peripheral is disabled