PDF《STM32F303xB/C Errata sheet》

9 1.2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Description On Cortex?-M4 with FPU core,

14 cycles are required to execute a VDIV or VSQRT instruction. This limitation is present when the following conditions are met: ? A VDIV or VSQRT is executed ? The destination register for VDIV or VSQRT is one of s0 - s15 ? An interrupt occurs and is taken ? The ISR being executed does not contain a floating point instruction ?

14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed In this case, if there are only one or two instructions inside the interrupt service routine, then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated, meaning that these registers hold incorrect out-of-date data. Workaround Two workarounds are applicable: ? Disable lazy context save of floating point state by clearing LSPEN to

0 (bit

30 of the FPCCR at address 0xE000EF34). ? Ensure that every ISR contains more than

2 instructions in addition to the exception return instruction. DocID023637 Rev

9 7/25 STM32F303xB/C STM32F303xB/C silicon limitations

24 2 STM32F303xB/C silicon limitations Table

4 gives quick references to all documented limitations. Legend for Table 4: A = workaround available;

N = no workaround available;

P = partial workaround available, '

-'

and grayed = fixed. Table 4. Summary of silicon limitations Links to silicon limitations Revision Z Revision Y Section 2.1: System limitations Section 2.1.1: SYSCFG_CFGR2, comparators and operational amplifiers control registers reset by APB2 reset A A Section 2.1.2: Data Read when the CPU accesses successively SRAM address A and SRAM address A + offset of

16 KBytes (0x4000) A - Section 2.1.3: Wakeup sequence from Standby mode when using more than one wakeup source A A Section 2.1.4: Full JTAG configuration without NJTRST pin cannot be used A A Section 2.1.5: CCM RAM write protection register SYSCFG_RCR not reset by system reset N N Section 2.2: ADC limitations Section 2.2.1: DMA Overrun in dual interleaved mode with single DMA channel A A Section 2.2.2: Sampling time shortened in JAUTO autodelayed mode A A Section 2.2.3: Injected queue of context is not available in case of JQM =

0 N N Section 2.2.4: Load multiple not supported by ADC interface A A Section 2.2.5: ADEN bit cannot be set immediately after the ADC calibration is done A A Section 2.2.6: Overrun flag might not be set when the converted data have not been read before new data are written A A Section 2.2.7: ADC differential mode common mode input range N N Section 2.2.8: Imprecise VREFINT calibration values N N Section 2.3: SPI peripheral limitations Section 2.3.1: Packing mode limitation at reception N N Section 2.3.2: SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer '

-1'

A A Section 2.3.3: BSY bit may stay high at the end of a SPI data transfer in sl........