PDF《A24C256》

2009 RELEASED, FEB

2012 RELEASED - -

5 - ? AC ELECTRICAL CHARACTERISTICS TA=-40oC to +85oC, VCC=+1.8V to +5.5V, CL=1 TTL gate and 100pF, unless otherwise specified. Parameter Symbol 1.8-volt 5.0-volt Unit MIN TYP MAX MIN TYP MAX Clock Frequency, SCL fSCL

400 400 KHz Clock Pulse Width Low tLOW 1.2 - 0.6 - us Clock Pulse Width High tHIGH 0.6 - 0.4 - us Noise Suppression Time tI -

50 50 ns Clock Low to Data Out Valid tAA 0.1 0.9 0.05 0.9 us Time the bus must be free before a new transmission can start tBUF 1.2 - 0.5 - us Start Hold Time tHD.STA 0.6 - 0.25 - us Start Setup Time tSU.STA 0.6 - 0.25 - us Data In Hold Time tHD.DAT

0 -

0 - us Data In Setup Time tSU.DAT

100 -

100 - ns Inputs Rise Time tR - 0.3 0.3 us Inputs Fall Time tF -

300 300 ns Stop Setup Time tSU.STO 0.6 - 0.25 - us Data Out Hold Time tDH

50 -

50 - ns Write Cycle Time tWR -

5 5 ms 5.0V, 25oC, Byte Mode Endurance 1M - - Write Cycles NOTE: This parameter is characterized and is not 100% tested. AC measurement conditions: RL(connects to VCC): 1.3KΩ(2.5V,5V),10KΩ(1.8V) Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall time: ≤50ns Input and output timing reference voltages: 0.5VCC The value of RL should be concerned according to the actual loading on the user'

s system. ? AiT Semiconductor Inc. www.ait-ic.com A24C256 TWO-WIRE SERIAL EEPROM 256K (32768 X 8) REV1.2 - MAY

2009 RELEASED, FEB

2012 RELEASED - -

6 - ? BLOCK DIAGRAM ? AiT Semiconductor Inc. www.ait-ic.com A24C256 TWO-WIRE SERIAL EEPROM 256K (32768 X 8) REV1.2 - MAY

2009 RELEASED, FEB

2012 RELEASED - -

7 - ? DETAILED INFORMATION DEVICE/PAGE ADDRESSES ( A1 and A0): The A1 and A0 pins are device address inputs that are hard wired for the A24C256. Four 256k devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The A24C256 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Table 1. Table1: Write Protect WP PIN STATUS PARTS OF THE ARRAY PROTECTED A24C256 At VCC Full (256K) Array At GND Normal Read/Write Operations ? AiT Semiconductor Inc. www.ait-ic.com A24C256 TWO-WIRE SERIAL EEPROM 256K (32768 X 8) REV1.2 - MAY

2009 RELEASED, FEB

2012 RELEASED - -

8 - ? FUNCTIONAL DESCRIPTION 1. Memory Organization The 256K is internally organized as

512 pages of

64 bytes each. Random word addressing requires a 15-bit data word address. 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure

1 on page 11). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure

2 on page 11). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure