PDF《A24C256》

2 on page 11) ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a

0 to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The A24C256 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to

9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. ? AiT Semiconductor Inc. www.ait-ic.com A24C256 TWO........