PDF《IRF9Z30, SiHF9Z30》

0 4

8 12

20 10

8 6

4 2

0 15 - ID, Drain Current (A) g f s , Tran s conductance ( S ) - VSD, Source-to-Drain Voltage (V) - I SD , Reverse Drain Current (A) TJ =

25 °C TJ =

150 °C

0 2

4 6

8 10

102 5

2 10

5 2

1 5

2 0.1 TJ, Junction Temperature (°C) V DS , Drain-to-Source Breakdown 1.25 Voltage (Normalized) 1.15 0.75 0.85 0.95 1.05 -

60 -

40 -

20 0

20 40

60 80

100 120

140 160 ID =

1 mA TJ, Junction Temperature (°C) R DS(on) , Drain-to-Source On Resistance 3.0 (Normalized) 2.4 0.0 0.6 1.2 1.8 -

60 -

40 -

20 0

20 40

60 80

100 120

140 160 ID = -

18 A VGS = -

10 V IRF9Z30, SiHF9Z30 www.vishay.com Vishay Siliconix S12-3048-Rev. A, 24-Dec-12

5 Document Number:

91459 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig.

9 - Typical Capacitance vs. Drain-to-Source Voltage Fig.

10 - Typical Gate Charge vs. Gate-to-Source Voltage Fig.

11 - Typical On-Resistance vs. Drain Current Fig.

12 - Maximum Drain Current vs. Case Temperature ? Capacitance (pF) - VDS, Drain-to-Source Voltage (V) Ciss Coss Crss

1 2

5 2

102 10

5 0

800 1200

1600 2000

400 VGS =

0 V, f =

1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Qg, Total Gate Charge (nC) - V GS , Gate-to-Source Voltage (V)

20 16

12 8

0 4 ID = -

18 A VDS = -

40 V For test circuit see figure

17 10

0 20

30 40

50 80 μs Pulse Test VGS = -

10 V VGS = -

20 V

0 12

24 36

48 60 0.4 0.8 1.2 1.6 2.0 - ID, Drain Current (A) R D S (on) , Drain to S ource on Re s i s tance 0.0 - I D , Drain Current (A) TC, Case Temperature (°C)

25 150

125 100

75 50 SiHF9Z32 SiHF9Z30

0 4

8 12

16 20 IRF9Z30, SiHF9Z30 www.vishay.com Vishay Siliconix S12-3048-Rev. A, 24-Dec-12

6 Document Number:

91459 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 13a - Unclamped Inductive Test Circuit Fig. 13b - Unclamped Inductive Load Test Waveforms Fig.

14 - Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse Duration Fig.

15 - Switching Time Test Circuit Fig.

16 - Gate Charge Test Circuit ? ? ? ? ? ? ? ? ? Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91459. Vary tp to obtain required peak IL VDD =

0 5

8 VDS EC =

0 75 BVDS - + VDD L EC DUT IL VGS = -

10 V tp 0.05 Ω VDSS IL tp VDD VDS

10 1 0.1 10-2 10-5 10-4 10-3 10-2 0.1

1 10 t1, Rectangular Pulse Duration (s) Thermal Response (Z thJC )

0 = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse (Thermal Response) PDM t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC - + RD D.U.T RG PS Vary IP to obtain required peak IL VGS = -

10 V tp

12 V battery 0.2 μF

50 kΩ 0.3 μF Current regulator - VDS (Isolated supply) Same type as D.U.T D.U.T D G S ID IG Current sampling resistor Current sampling resistor + VDS - 1.5 mA Package Information www.vishay.com Vishay Siliconix Revison: 14-Dec-15