PDF《四通道 1/2 H 桥驱动器集成电路 （IC）》

19 I Logic input reference ground voltage between VNEG and VM -

8 V. Connect to motor supply (8 V -

60 V). Both pins must be connected to same supply. VM 4,

11 - Main power supply Bypass to VNEG with a 10-?F (minimum) capacitor. Bypass to VNEG with a 0.47-μF 6.3-V V3P3OUT

15 O 3.3-V regulator output ceramic capacitor. Can be used to supply VREF. CP1

1 IO Charge pump flying capacitor Connect a 0.01-μF 100-V capacitor between CP1 and CP2. CP2

2 IO Charge pump flying capacitor Connect a 0.1-μF 16-V ceramic capacitor to VCP

3 IO High-side gate drive voltage VM. CONTROL Logic input controls state of OUT1. Internal IN1

27 I Channel

1 input pulldown. EN1

26 I Channel

1 enable Logic high enables OUT1. Internal pulldown. Logic input controls state of OUT2. Internal IN2

25 I Channel

2 input pulldown. EN2

24 I Channel

2 enable Logic high enables OUT2. Internal pulldown. Logic input controls state of OUT3. Internal IN3

23 I Channel

3 input pulldown. EN3

22 I Channel

3 enable Logic high enables OUT3. Internal pulldown. Logic input controls state of OUT4. Internal IN4

21 I Channel

4 input pulldown. EN4

20 I Channel

4 enable Logic high enables OUT4. Internal pulldown. Active-low reset input initializes internal logic nRESET

16 I Reset input and disables the H-bridge outputs. Internal pulldown. Logic high to enable device, logic low to enter nSLEEP

17 I Sleep mode input low-power sleep mode. Internal pulldown. STATUS Logic low when in fault condition (overtemp, nFAULT

18 OD Fault overcurrent, UVLO). Open-drain output. OUTPUT OUT1

5 O Output

1 OUT2

7 O Output

2 Connect to loads. OUT3

8 O Output

3 OUT4

10 O Output

4 NO CONNECT NC 12,

13 - No connect No connection to these pins (1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Copyright ? 2012, Texas Instruments Incorporated

3 DRV8844 ZHCSA48A CJULY 2012CREVISED OCTOBER

2012 www.ti.com.cn ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) (1) (2) VALUE UNIT VM Power supply voltage range C0.3 to

65 V Logic ground voltage range (LGND) C0.5 to VM -

8 V Digital pin voltage range LGND - 0.5 to LGND +

7 V Peak motor drive output current, t <

1 μS Internally limited A Continuous motor drive output current(3) 2.5 A TJ Operating virtual junction temperature range C40 to

150 °C Tstg Storage temperature range C60 to

150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absoluteCmaximumCrated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VNEG terminal, unless otherwise specified. (3) Power dissipation and thermal limits must be observed. THERMAL INFORMATION DRV8844 THERMAL METRIC(1) PWP UNITS

16 PINS θJA Junction-to-ambient thermal resistance(2) 31.6 θJCtop Junction-to-case (top) thermal resistance(3) 15.9 θJB Junction-to-board thermal resistance(4) 5.6 °C/W ψJT Junction-to-top characterization parameter(5) 0.2 ψJB Junction-to-board characterization parameter(6) 5.5 θJCbot Junction-to-case (bottom) thermal resistance(7) 1.4 (1) 有关传统和新的热 度量的更多信息,请参阅IC 封装热度量应用报告, SPRA953. (2) 在JESD51-2a 描述的环境中,按照 JESD51-7 的指定,在一个 JEDEC 标准高 K 电路板上进行仿真,从而获得自然 对流条件下的结至环 境热阻. (3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳(顶部)的热阻. 不存在特定的 JEDEC 标准测试,但 可在 ANSI SEMI 标准 G30-