PDF《TOSHIBA CMOS Digital Integrated》

TC74AC161,163P/F/FN/FT 2006-02-01

1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC161P,TC74AC161F,TC74AC161FN,TC74AC161FT TC74AC163P,TC74AC163F,TC74AC163FN,TC74AC163FT Synchronous Presettable 4-Bit Binary Counter TC74AC161P/F/FN/FT Asynchronous Clear TC74AC163P/F/FN/FT Synchronous Clear The TC74AC161 and

163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERs fabricated with silicon gate and double-layer metal wiring C2MOS technology.

They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of these IC'

s is synchronous to the rising edge of CK. The clear function of the TC74AC163 is synchronous to CK, while the TC74AC161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features ? High speed: fmax =

170 MHz (typ.) at VCC =

5 V ? Low power dissipation: ICC =

8 ?A (max) at Ta = 25°C ? High noise immunity: VNIH = VNIL = 28% VCC (min) ? Symmetrical output impedance: |IOH| = IOL =

24 mA (min) Capability of driving

50 ? transmission lines. ? Balanced propagation delays: tpLH ? ? tpHL ? Wide operating voltage range: VCC (opr) =

2 to 5.5 V ? Pin and function compatible with 74F161/163 Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOP16-P-300-1.27 : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC161P, TC74AC163P TC74AC161F, TC74AC163F TC74AC161FN, TC74AC163FN TC74AC161FT, TC74AC163FT TC74AC161,163P/F/FN/FT 2006-02-01

2 Pin Assignment IEC Logic Symbol Truth Table (Note) Inputs Outputs CLR (161) CLR (163) LOAD ENP ENT CK (161) CK (163) QA QB QC QD Function L L X X X X L L L L Reset to

0 H H L X X A B C D Preset Data H H H X L No Change No Count H H H L X No Change No Count H H H H H Count Up Count H X X X X No Change No Count Note : X: Don'

t care A, B, C, D: Logic level of data inputs Carry: Carry = ENT・QA・QB・QC・QD VCC

16 Carry Output QA QB

15 14

13 12

11 10 CLR

1 2

3 4

5 6

7 B C D ENP GND QC

8 LOAD

9 QD ENT (top view) CK A (9) (1) (10) (2) (7) ENP 1, 5D (1) CK (3) (4) B A (15) (14) QB (13) QA QC CT =

0 M1 LOAD CLR C (5) (6) D (12) QD (11) Carry Output ENT TC74AC161 CTRDIV

16 M2 G3 G4 C5/2, 3, 4+ 3CT =

15 (2) (4) (8) (9) (1) (10) (2) (7) ENP 1, 5D (1) CK (3) (4) B A (15) (14) QB (13) QA QC 5CT =

0 M1 LOAD CLR C (5) (6) D (12) QD (11) Carry Output ENT TC74AC163 CTRDIV

16 M2 G3 G4 C5/2, 3, 4+ 3CT =

15 (2) (4) (8) TC74AC161,163P/F/FN/FT 2006-02-01

3 Timing Chart COUNT INHIBIT

12 ASYNC CLEAR (161) SYNC CLEAR (163) PRESET

13 14

15 0

1 2 Carry Output QD QC QB QA ENT ENP CK D C B A LOAD CLR Data Inputs Outputs DON'

T CARE UNTIL LOAD GOES LOW TC74AC161,163P/F/FN/FT 2006-02-01

4 System Diagram Note: Truth table of internal F/F TC74AC161 TC74AC163 D CK R Q Q D CK R Q Q X X H L H X H L H L L L H L L L H H L H L H L H L X L No Change X L No Change X: Don'

t care CLR ENT

1 10 ENP LOAD

7 9 E E L

15 Carry Out

14 QA E E L (Note 2) L A

3 R Q D Q CK

13 QB E L (Note 2) L B

4 R Q D Q CK E

12 QC E L (Note 2) L C