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HDL SYNTHESIS FOR FPGAs ? DESIGN GUIDE ONLINE R

0401294 TABLE OF CONTENTS INDEX GO TO OTHER BOOKS HDL Synthesis for FPGAs Design Guide ―

0401294 01 i Contents Chapter

1 Getting Started Understanding HDL Design Flow for FPGAs.

1-1 Entering Your Design.1-2 Verifying Your Design.1-3 Floorplanning Your Design 1-3 Placing and Routing Your Design.1-3 Advantages of Using HDLs to Design FPGAs.1-3 Designing FPGAs with HDLs.1-5 Using VHDL.1-5 Comparing ASICs and FPGAs 1-5 Using Synthesis Tools 1-5 Using FPGA System Features.1-6 Designing Hierarchy 1-6 Specifying Speed Requirements 1-6 Installing Design Examples and Tactical Software 1-6 Software Requirements 1-7 SPARC and HP-PA Requirements 1-8 Disk Space Requirements 1-8 Xilinx Internet Site.1-8 Xilinx Technical Bulletin Board 1-9 Retrieving Tactical Software and Design Examples 1-9 From Xilinx Internet FTP Site 1-10 From Xilinx Technical Bulletin Board.1-11 Extracting the Files 1-11 Directory Tree Structure 1-12 Synopsys Startup File and Library Setup.1-14 Technical Support.1-14 Important Issues 1-14 Instantiating XNF Files in Verilog Designs.1-15 Block Names are Not Written by Default in Synopsys FPGA Compiler V3.3b 1-16 Creating MAP Files.1-16 Copyright

1995 Xilinx Inc. All Rights Reserved. ii Xilinx Development System HDL Synthesis for FPGAs Design Guide Chapter

2 HDL Coding Hints Comparing Synthesis and Simulation Results 2-2 Omit the Wait for XX ns Statement.2-2 Omit the ...After XX ns Statement.2-2 Use Case and If-Else Statements.2-2 Order and Group Arithmetic Functions 2-3 Omit Initial Values.2-3 Selecting VHDL Coding Styles.2-3 Selecting a Capitalization Style.2-4 Using Xilinx Naming Conventions.2-4 Naming Identifiers, Types, and Packages 2-5 Using Labels 2-5 Using Variables for Constants 2-6 Using Named and Positional Association 2-6 Managing Your Design 2-7 Creating Readable Code 2-7 Indenting Your Code.2-7 Using Empty Lines.2-7 Using Spaces.2-8 Breaking Long Lines of Code 2-8 Adding Comments 2-8 Using Std_logic Data Type 2-8 Declaring Ports 2-9 Minimizing the Use of Ports Declared as Buffers 2-9 Comparing Signals and Variables.2-10 Using Schematic Design Hints with HDL Designs 2-12 Barrel Shifter Design.2-12 Implementing Latches and Registers.2-16 Resource Sharing 2-20 Gate Reduction.2-25 Preset Pin or Clear Pin 2-27 Using Clock Enable Pin 2-30 Using If Statements.2-31 Using Case Statements 2-32 Using Nested_If Statements 2-33 Comparing If Statement and Case Statement 2-37 Chapter

3 HDL Coding for FPGAs Using Global Low-skew Clock Buffers 3-2 Inserting Clock Buffers.3-4 HDL Synthesis for FPGAs Design Guide iii Contents Instantiating Internal Global Clock Buffers.3-4 Using Dedicated Global Set/Reset Resource.3-4 Startup State.3-5 Preset vs. Clear 3-5 Increasing Performance with the GSR Net.3-6 Design Example without Dedicated GSR Resource.3-6 Design Example with Dedicated GSR Resource.3-8 Design Example with Dedicated GSR Resource and Additional Preset Signal 3-11 Encoding State Machines 3-13 Using Binary Encoding 3-14 Using Enumerated Type Encoding.3-16 Using One-Hot Encoding.3-17 Summary of Encoding Styles.3-18 Comparing Synthesis Results for Encoding Styles.3-19 Initializing the State Machine.3-20 Using Dedicated I/O Decoders 3-21 Instantiating X-BLOX Modules.3-25 Using X-BLOXGen.3-26 Syntax.3-27 Options 3-28 Output Files 3-28 X-BLOXGen Example.3-28 Using RPMs.3-32 Instantiating an RPM 3-34 Implementing Memory 3-36 Implementing XC4000 RAMs 3-36 Implementing XC4000 ROMs.3-36 Using MemGen.3-38 Implementing Boundary Scan (JTAG 1149.1)3-40 Instantiating the Boundary Scan Symbol.3-40 Implementing Logic with IOBs 3-42 XC4000/A/D IOBs.3-43 Inputs.3-43 Outputs.3-43 XC4000/D Slew Rate.3-43 XC4000A Slew Rate.3-44 XC4000H IOBs 3-44 Inputs.3-44 Outputs.3-44 XC4000H Slew Rate.3-45 iv Xilinx Development System HDL Synthesis for FPGAs Design Guide Instantiating Bidirectional I/O 3-45 Moving Registers into the IOB 3-46 Using Unbonded IOBs (XC4000/A/D Only)3-48 Implementing Multiplexers with Tristate Buffers.3-50 Setting Timing Constraints.3-53 Using the Synthesis Tool 3-53 Using PPR Command Line Options.3-54 Using A Constraints File 3-55 Using TIMESPEC and TIMEGRP Commands 3-55 Using TIMESPEC and TIMEGRP Constraints File Statements.3-56 Using MakeTNM and AddTNM.3-57 Adding TNMs.3-57 Creating A TNM Control File Without Using MakeTNM..... 3-65 Adding TNMs to Signals 3-66 Chapter