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4 Floorplanning Your Design Using the Floorplanner.4-2 Creating a MAP File.4-2 Using XMake 4-2 Using PPR 4-2 Using Prep for Floorplanner Command 4-2 Overview of Floorplanner Windows 4-3 Task Window 4-3 Design Window.4-3 Floorplan Window.4-4 Deciding What Elements to Floorplan.4-5 Running the Floorplanner and Opening a File.4-6 Using the Command Line 4-6 Using the Floorplanner Task Window.4-6 Setting Boundaries in the Floorplan Window.4-8 Floorplanning RPMs, RAMs, and ROMs.4-9 RPM and RAM/ROM Example.4-10 Floorplanning Tristate Buffers.4-13 BUFT Example.4-14 Floorplanning BUFT Example.4-16 Comparing Hierarchical and Flat Designs.4-20 Method 1: Compiling Flat without X-BLOX 4-24 Method 2: Compiling Flat with X-BLOX 4-26 Method 3: Compiling with Hierarchy and without X-BLOX.4-26 HDL Synthesis for FPGAs Design Guide v Contents Method 4: Compiling with Hierarchy and X-BLOX.4-27 Floorplanning to Reduce Routing Congestion 4-28 Positioning and Aligning Buses 4-29 Aligning Structures Along Buses 4-29 Floorplanning RAMs to Reduce Routing Congestion 4-34 Chapter

5 Building Design Hierarchy Using the Synthesis Tool 5-2 Modifying Design Hierarchy for PPR 5-3 Top Design Example.5-4 Compiling Top Design as One Flat Module 5-7 Compiling Top Design Using Original Hierarchy 5-8 Floorplanning RPMs 5-8 Meeting Speed Requirements 5-10 Compiling Top Design After Modifying the Hierarchy 5-11 Evaluating A New Hierarchy.5-15 Defining and Compiling the New Hierarchy.5-15 Setting Boundaries and Floorplanning the Modules.5-19 Floorplanning Structured Cells 5-21 Placing and Routing the Top Design 5-22 Adding Probe Points to Debug a Design 5-23 Comparing Top Design Methodologies 5-24 Flat Design 5-24 Original Design Hierarchy.5-24 Modified Hierarchy.5-24 Chapter

6 Understanding High-Density Design Flow Step 1: Estimating Your Design Size.6-4 Determining Device Utilization.6-5 Step 2: Evaluating Your Design for Coding Style and System Features.6-7 Step 3: Modifying Your Design Hierarchy.6-8 Estimating Area Utilization.6-9 Creating a New Hierarchy.6-11 Step 4: Synthesizing and Optimizing Your Design 6-11 Step 5: Translating Your Design and Adding Group TimeSpecs. 6-12 Translating Your Design 6-12 Adding Timing Specifications.6-13 Using the Synthesis Tool.6-13 Using PPR Command Line Options 6-13 Using A Constraints File 6-13 vi Xilinx Development System HDL Synthesis for FPGAs Design Guide Step 6: Building Your Design Hierarchy.6-15 Step 7: Floorplanning Your Design 6-15 Creating a MAP File.6-15 Using XMake 6-16 Using PPR 6-16 Using Prep for Floorplanner Option.6-16 Floorplanning Design Components.6-16 Writing a Constraints File.6-17 Step 8: Placing and Routing Your Design.6-17 Using PPR Options.6-18 Determining If PPR Can Route Your Design 6-19 Step 9: Evaluating the Results.6-19 Evaluating Module Placement with the Floorplanner.6-20 Modifying Design Placement 6-25 Using Guided Design 6-26 Using Iterative Guided Design 6-27 Using Incremental Guided Design 6-27 Using XDE 6-27 Effectively Using Guided Design.6-28 Understanding Guided Design for XC4000 Designs.6-28 Adding a New Module to Your Design.6-28 Making a Design Change to a Module.6-29 Appendix A Accelerate FPGA Macros with One-Hot Approach Appendix B Top Design Scripts VHDL Script Files.B-1 Verilog Script Files B-6 Appendix C Tactical Software and Design Examples Tactical Software.C-1 Design Examples C-2 Index i Trademark Information HDL Synthesis for FPGAs Design Guide ―

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1 Getting Started Hardware Description Languages (HDLs) are used to describe the behavior and structure of system and circuit designs. This chapter provides a general overview of designing FPGAs with HDLs. It also includes design hints for the novice HDL user and for the experienced user who is designing FPGAs for the ?rst time. System requirements and installation instructions are also provided. To learn more about designing FPGAs with HDLs, Xilinx recommends that you enroll in the appropriate training classes offered by Xilinx and by the vendors of synthesis software. Understanding FPGA architecture allows you to create HDL code that effectively uses FPGA system features. Understanding HDL Design Flow for FPGAs Application Speci?c Integrated Circuit (ASIC) designs or sections of these designs that are targeted for FPGAs are often created with HDLs. However, the design ?ow for processing ASIC HDL code is slightly different from the ?ow used to process HDL code written speci?cally for FPGAs. Figure 1-1 shows the design ?ow for an FPGA design. This design ?ow includes the following steps. 1. Creating your FPGA design with an HDL. 2. Performing a Register Transfer Level (RTL) simulation of your design. 3. Synthesizing your design. 4. Creating a Xilinx Netlist File (XNF) ?le. 5. Performing a functional simulation of your design. HDL Synthesis for FPGAs Design Guide 1-2 Xilinx Development System 6. Floorplanning your design. This step is optional. 7. Placing and routing (implementing) your design. 8. Performing a timing simulation of your design. Figure 1-1 HDL Flow Diagram for a New Design The design ?ow for ASICs differs depending on the quality of the existing code. You must analyze the ASIC design to determine if the code meets speed and area requirements for FPGAs. Additionally, you should structure the design hierarchy for FPGA implementation. Entering Your Design When coding in HDL, you should create ef?cient code that utilizes FPGA system features and is structured into hierarchical blocks. These topics are described in detail in this manual. HDL Synthesis Floorplanning Work Flow RTL HDL Simulation Functional Gate-level Simulation Timing Gate-level Simulation X4915 Structured VHDL or Verilog Hierarchical design.xnf Place and Route Getting Started HDL Synthesis for FPGAs Design Guide 1-3 Verifying Your Design You can behaviorally simulate your HDL designs to test system and device functionality before synthesis. After simulation, your design is synthesized and optimized for the target device. The hierarchical HDL code is then written as XNF ?les. After placement and routing, the design is simulated with the actual gate and wire delays. Xilinx recommends that you perform an RTL or functional simulation of your design before ?oorplanning the cells (CLBs, IOBs, BUFTs) into the FPGA. If you ?nd functional errors during a simulation performed after ?oorplanning, you must correct your code, resynthesize your design, and repeat the ?oorplanning process. The Xilinx Floorplanner builds a constraints ?le that includes the cell names in your design. If the cell names change, as they might if you resynthesize your design, the names in the constraints ?le are no longer correct. Floorplanning Your Design Floorplanning is an optional step in the design ?ow. You can improve device density and increase the speed of critical paths by ?oorplanning parts or all of your design with the Xilinx Floorplanner. You can generate a constraints ?le that is read by PPR. Refer to the Floorplanning Your Design chapter in this manual for more information on ?oorplanning. Placing and Routing Your Design After ?oorplanning, run PPR to place and route your design. PPR reads the constraints ?le generated by the F........