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64 Kbytes ? Built-in RAM capacity ? Main RAM MB91F583:

32 Kbytes MB91F584:

48 Kbytes MB91F585:

48 Kbytes ? Backup RAM

8 Kbytes ? General-purpose port: MB91F583AM/F584AM/F585AM

76 ports Including eight I

2 C pseudo open drain corresponding ports MB91F583AS/F584AS/F585AS 44ports Including two I

2 C pseudo open drain corresponding ports Document Number: 002-04665 Rev *A Page

2 of

175 MB91580M/S Series ? DMA controller ? Up to

8 channels can be started simultaneously. ?

2 transfer factors (Internal peripheral request and software) ? External interrupt input MB91F583AM/F584AM/F585AM:

8 channels MB91F583AS/F584AS/F585AS:

7 channels Level ( H / L ) or edge detection (rising or falling) enabled ? Multi-function serial communication (built-in transmission/reception FIFO memory) MB91F583AM/F584AM/F585AM:

4 channels MB91F583AS/F584AS/F585AS:

2 channels ? UART (Asynchronous serial interface) ? Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory ? Parity or no parity is selectable. ? Built-in dedicated baud rate generator ? An external clock can be used as the transfer clock ? Parity, frame, and overrun error detection functions provided ? DMA transfer supported ? CSIO (Synchronous serial interface) ? Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory ? SPI supported;

master and slave systems supported;

5 to 16, 20, 24, 32-bit data length can be set. ? Built-in dedicated baud rate generator (Master operation) ? An external clock can be entered. (Slave operation) ? Overrun error detection function is provided. ? Built-in chip selection function ? DMA transfer supported ? LIN interface (v2.1) ? Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory ? LIN protocol revision2.1 supported. ? Master and slave systems supported ? Framing error and overrun error detection ? LIN sync break generation and detection;

LIN sync delimiter generation ? Built-in dedicated baud rate generator ? An external clock can be adjusted by the reload counter. ? DMA transfer supported ? I

2 C ? MB91F583AM/F584AM/F585AM: Supported for

3 channels: ch.0,ch.2,and ch.3 MB91F583AS/F584AS/F585AS: Supported for

1 channel: ch.0 ? Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory ? Standard mode (Max.

100 kbps) / high-speed mode (Max.

400 kbps) supported ? DMA transfer supported (for transmission only) ? CAN controller (CAN) MB91F583AM/F584AM/F585AM:

2 channels MB91F583AS/F584AS/F585AS:

1 channel ? Transfer speed: Up to 1Mbps ? 64-transmission/reception message buffering ? FlexRay controller MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584A MJ/F585AMJ/ F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F58 5ASJ:

1 unit (ch.A/ch.B) ? FlexRay Specifications Version 2.1 supported ? Up to

128 message buffers ? 8K bytes of message RAM ? Variable length of message buffers ? Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception FIFO memory ? Host access to the message buffer via input and output buffers ? Filtering for slot counter, cycle counter and channels ? Maskable interrupts are supported ? PPG:

16 bits *

6 channels ? Reload timer:

16 bits *

4 channels ? A/D converter (successive approximation type) ? 12-bit resolution MB91F583AM/F584AM/F585AM:

3 units (23 channels) MB91F583AS/F584AS/F585AS:

3 units (17 channels) ? Conversion time:

1 ?s ? Free-run timer

16 bits *