PDF《MCP3204/3208》

100 50 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution

12 bits Integral Nonlinearity INL ― ― ±0.75 ±1.0 ±1 ±2 LSB MCP3204/3208-B MCP3204/3208-C Differential Nonlinearity DNL ― ±0.5 ±1 LSB No missing codes over-temperature Offset Error ― ±1.25 ±3 LSB Gain Error ― ±1.25 ±5 LSB Dynamic Performance Total Harmonic Distortion ― -82 ― dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) ―

72 ― dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range ―

86 ― dB VIN = 0.1V to 4.9V@1 kHz Reference Input Voltage Range 0.25 ― VDD V Note

2 Current Drain ― ―

100 0.001

150 3.0 ?A ?A CS = VDD = 5V Analog Inputs Input Voltage Range for CH0- CH7 in Single-Ended Mode VSS ― VREF V Input Voltage Range for IN+ in pseudo-differential Mode IN- ― VREF+IN- Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below

10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 Maintaining Minimum Clock Speed , Maintaining Minimum Clock Speed , for more information. ?

2008 Microchip Technology Inc. DS21298E-page

3 MCP3204/3208 Input Voltage Range for IN- in pseudo-differential Mode VSS-100 ― VSS+100 mV Leakage Current ― 0.001 ±1 ?A Switch Resistance ―

1000 ― ? See Figure 4-1 Sample Capacitor ―

20 ― pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH 0.7 VDD ― ― V Low Level Input Voltage VIL ― ― 0.3 VDD V High Level Output Voltage VOH 4.1 ― ― V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL ― ― 0.4 V IOL =

1 mA, VDD = 4.5V Input Leakage Current ILI -10 ―

10 ?A VIN = VSS or VDD Output Leakage Current ILO -10 ―

10 ?A VOUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN,COUT ― ―

10 pF VDD = 5.0V (Note 1) TA = 25°C, f =

1 MHz Timing Parameters Clock Frequency fCLK ― ― ― ― 2.0 1.0 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI

250 ― ― ns Clock Low Time tLO

250 ― ― ns CS Fall To First Rising CLK Edge tSUCS

100 ― ― ns Data Input Setup Time tSU

50 ― ― ns Data Input Hold Time tHD

50 ― ― ns CLK Fall To Output Data Valid tDO ― ―

200 ns See Figures 1-2 and 1-3 CLK Fall To Output Enable tEN ― ―

200 ns See Figures 1-2 and 1-3 CS Rise To Output Disable tDIS ― ―

100 ns See Figures 1-2 and 1-3 CS Disable Time tCSH

500 ― ― ns DOUT Rise Time tR ― ―

100 ns See Figures 1-2 and 1-3 (Note 1) DOUT Fall Time tF ― ―

100 ns See Figures 1-2 and 1-3 (Note 1) Power Requirements Operating Voltage VDD 2.7 ― 5.5 V Operating Current IDD ― ―

320 225

400 ― ?A VDD=VREF = 5V, DOUT unloaded VDD=VREF = 2.7V, DOUT unloaded Standby Current IDDS ― 0.5 2.0 ?A CS = VDD = 5.0V ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C,fSAMPLE =

100 ksps and fCLK = 20*fSAMPLE Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below

10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 Maintaining Minimum Clock Speed , Maintaining Minimum Clock Speed , for more information. MCP3204/3208 DS21298E-page