PDF《XRD8785》

EXAR Corporation,

48720 Kato Road, Fremont, CA

94538 ? (510) 668-7000 ? FAX (510) 668-7017 Rev.

3.00 XRD8785 CMOS 8-Bit High Speed Analog-to-Digital Converter April

2002 FEATURES ? 8-Bit Resolution ? Up to

20 MHz Sampling Rate ? Internal S/H Function ? Single Supply: 5V ? VIN DC Range: 0V to VDD ? VREF DC Range: 1V to VDD ? Low Power: 75mW typ. (excluding reference) ? Latch-Up Free ? ESD Protection: 2000V Minimum GENERALDESCRIPTION The XRD8785 is an 8-bit Analog-to-Digital Converter. Designed using an advanced 5V CMOS process, this part offers excellent performance, low power con- sumption, and latch-up free operation. This device uses a two-step flash architecture to maintain low power consumption at high conversion rates. The input circuitry of the XRD8785 includes an on-chip S/H function which allows the user to digitize analoginputsignalsbetweenAGNDand AVDD.Careful design and chip layout have achieved a low analog input capacitance. This reduces "kickback" and eases the requirements of the buffer/amplifier used to drive the XRD8785. The designer can choose the internally generated reference voltages by connecting VRB to ? 20-Pin Package Available: XRD8775 ? 3V Version: XRD87L85 APPLICATIONS ? Digital Color Copiers ? Cellular Telephones ? CCDs and Scanners ? Video Capture Boards VRBS and VRT to VRTS, or provide external reference voltages to the VRB andVRT pins.Theinternalreference generates 0.6V at VRB and 2.6 V at VRT. Providing external reference voltages allows easy interface to any input signal range between AGND and AVDD. This also allows the system to adjust these voltages to cancelzeroscaleandfullscaleerrors,ortochangethe input range as needed. The device operates from a single +5V supply. Power consumption is 75mW at FS = 15MHz. Specified for operation over the commercial/industrial (C40 to +85°C)temperaturerange,theXRD8785isavailablein Plastic Dual-in-line(PDIP),SurfaceMount(SOIC)and Small Outline (SOP) packages in EIAJ and JEDEC. SIMPLIFIED BLOCK AND TIMING DIAGRAM XRD8785

2 Rev. 3.00 24-Pin PDIP (300 MIL) - P24 ORDERINGINFORMATION PINCONFIGURATIONS See Packaging Section for Package Dimensions 24-Pin SOP (EIAJ, 5.4mm) C K24 24-Pin SOIC (Jedec,

300 MIL) C D24 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION

1 OE Output Enable

2 DGND Digital Ground

3 DB0 Data Output Bit

0 (LSB)

4 DB1 Data Output Bit

1 5 DB2 Data Output Bit

2 6 DB3 Data Output Bit

3 7 DB4 Data Output Bit

4 8 DB5 Data Output Bit

5 9 DB6 Data Output Bit

6 10 DB7 Data Output Bit

7 (MSB)

11 DVDD Digital Power Supply

12 CLK Sampling Clock Input PIN NO. NAME DESCRIPTION

13 DVDD Digital Power Supply

14 AVDD Analog Power Supply

15 AVDD Analog Power Supply

16 VRTS Generates 2.6 V if tied to VRT

17 VRT Top Reference

18 AVDD Analog Power Supply

19 VIN Analog Input

20 AGND Analog Ground

21 AGND Analog Ground

22 VRBS Generates 0.6 V if tied to VRB

23 VRB Bottom Reference

24 DGND Digital Ground Package Temperature Part No. DNL INL Type Range (LSB) (LSB) SOIC (Jedec) C40 to +85°C XRD8785AID +/- 0.75 +/-1.5 SOP (EIAJ) C40 to +85°C XRD8785AIK +/- 0.75 +/-1.5 Plastic Dip (300MIL) C40 to +85°C XRD8785AIP +/- 0.75 +/-1.5 XRD8785

3 Rev. 3.00 ELECTRICALCHARACTERISTICSTABLE UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 5V, FS = 15MHZ (50% DUTY CYCLE), VRT = 2.6V, VRB = 0.6V, TA = 25°C 25°C Parameter Symbol Min Typ Max Units TestConditions/Comments KEYFEATURES Resolution

8 Bits SamplingRate FS 0.1

15 20 MHz ACCURACY Differential Non-Linearity DNL +/-0.75 LSB @ 15MHz Differential Non-Linearity DNL +/-0.5 LSB @ 10MHz Integral Non-Linearity INL +/-1.5 LSB Best Fit Line (Max INL C Min INL)/2 Zero Scale Error EZS +3 LSB Full Scale Error EFS -2 LSB REFERENCEVOLTAGES Positive Ref. Voltage VRT 2.6 AVDD V Negative Ref. Voltage VRB AGND 0.6 V Differential Ref. Voltage3 V REF 1.0 AVDD V VREF = VRT C VRB Ladder Resistance RL