编辑: 梦里红妆 | 2019-07-04 |
6 AGND G Analog ground.
7 SS I Soft Start. An external capacitor and an internal 10-?A current source set the rise time of the error amp reference. The SS pin is held low when VCC is less than the VCC undervoltage threshold (<
3.7 V), when the UVLO pin is low (<
1.23 V), when EN is low (<
0.5 V) or when thermal shutdown is active.
8 FB I Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.
9 COMP O Output of the internal error amplifier. The loop compensation network should be connected between COMP and the FB pin.
10 VOUT I Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.
11 SYNC I Sync input for switching regulator synchronization to an external clock.
12 CS I Current sense input. Connect to the diode side of the current sense resistor.
13 CSG I Current sense ground input. Connect to the ground side of the current sense resistor.
14 PGND G Power Ground.
15 LO O Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.
16 VCC P/I/O Output of the bias regulator. Locally decouple to PGND using a l........