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250 mV BW = 100Hz to 100kHz, VIN = 2.2V, VN Output noise voltage

86 ?VRMS VOUT = 1.2V, IOUT = 1mA VSET high (output VOUT(LOW) VHI 1.2 VIN V selected), or EN high (enabled) VSET low (output VOUT(HIGH) VLO

0 0.4 V selected), or EN low (disabled) ICL Output current limit VOUT = 0.90 * VOUT(NOM)

150 230

400 mA IOUT = 0mA 1.0 1.3 ?A IGND Ground pin current IOUT = 150mA

8 ?A VEN ≤ 0.4V, 2.2V ≤ VIN <

5.5V, ISHDN Shutdown current (IGND)

18 130 nA TJ = C40°C to +100°C IVSET VSET pin current VEN = VVSET = 5.5V

70 nA IEN EN pin current VEN = VVSET = 5.5V

40 nA FB pin current(6) IFB VIN = 5.5V, VOUT = 1.2V, IOUT = 100?A

10 nA (adjustable version only) f = 10Hz

40 dB VIN = 4.3V, PSRR Power-supply rejection ratio VOUT = 3.3V, f = 100Hz

20 dB IOUT = 150mA f = 1kHz

15 dB VOUT transition time (high-to-low) VOUT_LOW = 2.2V, VOUT(HIGH) = 3.3V, tTR(H→L)

800 ?s VOUT = 97% * VOUT(HIGH) IOUT = 10mA VOUT transition time (low-to-high) VOUT_HIGH = 3.3V, VOUT(LOW) = 2.2V, tTR(L→H)

800 ?s VOUT = 97% * VOUT(LOW) IOUT = 10mA COUT = 1.0?F, VOUT = 10% VOUT(NOM) to tSTR Startup time(7)

500 ?s VOUT = 90% VOUT(NOM) IOUT = 150mA, COUT = 1.0?F, VOUT = 2.8V, tSHDN Shutdown time(8) VOUT = 90% VOUT(NOM) to VOUT = 10% 500(9) ?s VOUT(NOM) Shutdown, temperature increasing +160 °C TSD Thermal shutdown temperature Reset, temperature decreasing +140 °C TJ Operating junction temperature C40 +125 °C (1) The output voltage for VSET = low/high is programmed at the factory. (2) Adjustable version only. (3) No VSET pin on the adjustable version. (4) No dynamic voltage scaling on the adjustable version. (5) VDO is not measured for devices with VOUT(NOM) <

2.3V because minimum VIN = 2.2V. (6) The TPS78101 FB pin is tied to VOUT. Adjustable version only. (7) Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)). (8) Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)). (9) See Shutdown in the Application Information section for more details. Copyright ? 2008, Texas Instruments Incorporated Submit Documentation Feedback

3 FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS TPS781 Series SBVS102BCMARCH 2008CREVISED MAY

2008 www.ti.com (1) Feedback pin (FB) for adjustable versions;

VSET for fixed voltage versions. (1) It is recommended that the SON package thermal pad be connected to ground. Table 1. TERMINAL FUNCTIONS TERMINAL NAME DRV DDC DESCRIPTION Regulated output voltage pin. A small (1?F) ceramic capacitor is needed from this pin to OUT

1 5 ground to assure stability. See the Input and Output Capacitor Requirements in the Application Information section for more details. N/C

2 ― Not connected. Feedback pin (FB) for adjustable versions;

VSET for fixed voltage versions. Driving the select VSET/FB

3 4 pin (VSET) below 0.4V selects preset output voltage high. Driving the VSET pin over 1.2V selects preset output voltage low. Driving the enable pin (EN) over 1.2V turns on the regulator. Driving this pin below 0.4V puts EN

4 3 the regulator into shutdown mode, reducing operating current to 18nA typical. GND

5 2 Ground pin. Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input IN

6 1 capacitor = 1.0?F. Both input and output capacitor grounds should be tied back to the IC ground with no significant impedance between them. Thermal pad Thermal pad ― It is recommended that the SON package thermal pad be connected to ground.

4 Submit Documentation Feedback Copyright ? 2008, Texas Instruments Incorporated TYPICAL CHARACTERISTICS TPS781 Series www.ti.com SBVS1........