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0 (Control) Features C End Points 1,2,3,4 (Control, Bulk, Interrupt or C Hardware-Assisted Native Command ISOC) Rx and Tx Queueing (NCQ) for up to

32 Entries ? One Multichannel Audio Serial Port: C Supports Port Multiplier and C Transmit/Receive Clocks Command-Based Switching C Two Clock Zones and

16 Serial Data Pins ? Real-Time Clock With

32 KHz Oscillator and C Supports TDM, I2S, and Similar Formats Separate Power Rail C DIT-Capable ? Three 64-Bit General-Purpose Timers (Each C FIFO buffers for Transmit and Receive configurable as Two 32-Bit Timers) ? Two Multichannel Buffered Serial Ports: ? One 64-bit General-Purpose/Watchdog Timer C Transmit/Receive Clocks (Configurable as Two 32-bit General-Purpose C Supports TDM, I2S, and Similar Formats Timers) C AC97 Audio Codec Interface ? Two Enhanced Pulse Width Modulators (eHRPWM): C Telecom Interfaces (ST-Bus, H100) C Dedicated 16-Bit Time-Base Counter With C 128-channel TDM Period And Frequency Control C FIFO buffers for Transmit and Receive C

6 Single Edge,

6 Dual Edge Symmetric or

3 ? 10/100 Mb/s Ethernet MAC (EMAC): Dual Edge Asymmetric Outputs C IEEE 802.3 Compliant C Dead-Band Generation C MII Media Independent Interface C PWM Chopping by High-Frequency Carrier C RMII Reduced Media Independent Interface C Trip Zone Input C Management Data I/O (MDIO) Module ? Three 32-Bit Enhanced Capture Modules ? Video Port Interface (VPIF): (eCAP): C Two 8-bit SD (BT.656), Single 16-bit or Single C Configurable as

3 Capture Inputs or

3 Raw (8-/10-/12-bit) Video Capture Channels Auxiliary Pulse Width Modulator (APWM) C Two 8-bit SD (BT.656), Single 16-bit Video outputs Display Channels C Single Shot Capture of up to Four Event ? Universal Parallel Port (uPP): Time-Stamps C High-Speed Parallel Interface to FPGAs and ? 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) Data Converters [ZWT Suffix], 0.80-mm Ball Pitch C Data Width on Each of Two Channels is 8- to ? Extended Temperature

2 AM1810 ARM Microprocessor Copyright ? 2010C2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1810 AM1810 www.ti.com SPRS709B CNOVEMBER 2010CREVISED DECEMBER

2011 1.2 Description The device is a Low-power industrial applications processor based on ARM926EJ-S? that is specifically targeted for Profibus applications. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor

15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module;

one USB2.0 OTG interface;

one USB1.1 OHCI interface;

two inter-integrated circuit (I2C) Bus interfaces;

one multichannel audio serial port (McASP) with

16 serializers and FIFO buffers;

two multichannel buffered serial ports (McBSP) with FIFO buffers;

two SPI interfaces with multiple chip selects;