PDF《HC11》

HC11 MC68HC11D3 Technical Data TECHNICAL DATA iii TABLE OF CONTENTS Paragraph Number Page Number Section

1 INTRODUCTION 1.

1 Features.1-1 1.2 Structure 1-1 Section

2 PIN DESCRIPTIONS 2.1 VDD, VSS, and EVSS.2-2 2.2 Reset (RESET)2-2 2.3 Crystal Driver and External Clock Input (XTAL, EXTAL)2-3 2.4 E-Clock Output (E)2-4 2.5 Interrupt Request (IRQ)2-4 2.6 Non-Maskable Interrupt (XIRQ)2-4 2.7 MODA and MODB (MODA/LIR,and MODB/VSTBY)2-5 2.8 PD6/AS 2-5 2.9 PD7/R/W 2-5 2.10 Port Signals 2-6 2.10.1 Port A 2-7 2.10.2 Port B 2-7 2.10.3 Port C 2-7 2.10.4 Port D 2-8 Section

3 CENTRAL PROCESSING UNIT 3.1 CPU Registers 3-1 3.1.1 Accumulators A, B, and D 3-2 3.1.2 Index Register X (IX)3-2 3.1.3 Index Register Y (IY)3-2 3.1.4 Stack Pointer (SP)3-2 3.1.5 Program Counter (PC)3-4 3.1.6 Condition Code Register (CCR)3-4 3.1.6.1 Carry/Borrow (C)3-4 3.1.6.2 Overflow (V)3-5 3.1.6.3 Zero (Z)3-5 3.1.6.4 Negative (N)3-5 3.1.6.5 Interrupt Mask (I)3-5 3.1.6.6 Half Carry (H)3-5 3.1.6.7 X Interrupt Mask (X)3-5 3.1.6.8 Stop Disable (S)3-6 3.2 Data Types.3-6 3.3 Opcodes and Operands.3-6 3.4 Addressing Modes 3-6 3.4.1 Immediate.3-7 3.4.2 Direct 3-7 3.4.2.1 Extended 3-7 3.4.2.2 Indexed.3-7 3.4.2.3 Inherent 3-7 3.4.2.4 Relative.3-7 3.5 Instruction Set 3-8 iv TECHNICAL DATA Table of Contents (Cont.) Paragraph Number Page Number Section

4 OPERATING MODES AND ON-CHIP MEMORY 4.1 Operating Modes 4-1 4.1.1 Single-Chip Mode 4-1 4.1.2 Expanded Multiplexed Mode 4-1 4.1.3 Special Test Mode 4-2 4.1.4 Bootstrap Mode 4-2 4.2 Memory Map 4-3 4.2.1 Priority and Mode Select Register 4-6 4.2.2 System Initialization 4-8 4.2.2.1 CONFIG Register 4-8 4.2.2.2 INIT Register 4-9 4.2.2.3 OPTION Register 4-10 Section

5 RESETS AND INTERRUPTS 5.1 Resets 5-1 5.1.1 Power-On Reset 5-1 5.1.2 External Reset (RESET)5-1 5.1.3 COP Reset 5-1 5.1.4 Clock Monitor Reset 5-2 5.1.5 Option Register.5-3 5.1.6 CONFIG Register 5-4 5.2 Effects of Reset 5-4 5.2.1 CPU 5-4 5.2.2 Memory Map.5-4 5.2.3 Parallel I/O 5-5 5.2.4 Timer 5-5 5.2.5 Real-Time Interrupt.5-5 5.2.6 Pulse Accumulator 5-5 5.2.7 COP 5-6 5.2.8 SCI 5-6 5.2.9 SPI 5-6 5.2.10 System 5-6 5.3 Reset and Interrupt Priority 5-6 5.3.1 Highest Priority Interrupt and Miscellaneous Register 5-7 5.4 Interrupts 5-8 5.4.1 Interrupt Recognition and Register Stacking 5-9 5.4.2 Non-Maskable Interrupt Request XIRQ 5-10 5.4.3 Illegal Opcode Trap 5-10 5.4.4 Software Interrupt 5-11 5.4.5 Maskable Interrupts 5-11 5.4.6 Reset and Interrupt Processing 5-11 5.5 Low-Power Operation 5-16 5.5.1 WAIT.5-16 5.5.2 STOP 5-17 Section

6 PARALLEL I/O 6.1 Port A 6-1 6.2 Port B 6-1 6.3 Port C.6-2 TECHNICAL DATA v Table of Contents (Cont.) Paragraph Number Page Number 6.4 Port D.6-2 6.5 Parallel I/O Control Register (PIOC)6-4 Section

7 SERIAL COMMUNICATIONS INTERFACE 7.1 Data Format 7-1 7.2 Transmit Operation 7-1 7.3 Receive Operation 7-2 7.4 Wake-up Feature 7-4 7.4.1 Idle-Line Wakeup 7-4 7.4.2 Address-Mark Wakeup 7-4 7.5 SCI Error Detection 7-5 7.6 SCI Registers.7-5 7.6.1 Serial Communications Data Register (SCDR)7-5 7.6.2 Serial Communications Control Register

1 (SCCR1)7-5 7.6.3 Serial Communications Control Register

2 (SCCR2)7-6 7.6.4 Serial Communication Status Register (SCSR)7-7 7.6.5 Baud Rate Register (BAUD)7-8 7.7 Status Flags and Interrupts 7-10 Section

8 SERIAL PERIPHERAL INTERFACE 8.1 Functional Description 8-1 8.2 SPI Transfer Formats.8-2 8.2.1 Clock Phase and Polarity Controls 8-3 8.3 SPI Signals.8-3 8.3.1 Master In Slave Out 8-4 8.3.2 Master Out Slave In 8-4 8.3.3 Serial Clock 8-4 8.3.4 Slave Select 8-4 8.4 SPI System Errors 8-4 8.5 SPI Registers 8-5 8.5.1 Serial Peripheral Control 8-6 8.5.2 Serial Peripheral Status 8-7 8.5.3 Serial Peripheral Data I/O.8-7 Section