PDF《HC11》

9 TIMING SYSTEM 9.1 Timer Structure 9-3 9.2 Input Capture 9-4 9.2.1 Timer Control

2 Register 9-5 9.2.2 Timer Input Capture Registers 9-6 9.2.3 Timer Input Capture 4/Output Compare

5 Register 9-6 9.3 Output Compare.9-6 9.3.1 Timer Output Compare Registers.9-7 9.3.2 Timer Compare Force Register 9-8 9.3.3 Output Compare Mask Registers 9-8 9.3.4 Output Compare

1 Data Register 9-9 9.3.5 Timer Counter Register 9-9 9.3.6 Timer Control

1 Register 9-9 9.3.7 Timer Interrupt Mask

1 Register.9-10 9.3.8 Timer Interrupt Flag

1 Register.9-10 vi TECHNICAL DATA Table of Contents (Cont.) Paragraph Number Page Number 9.3.9 Timer Interrupt Mask

2 Register.9-11 9.3.10 Timer Interrupt Flag

2 Register.9-12 9.4 Real-Time Interrupt 9-12 9.4.1 Timer Interrupt Flag

2 Register.9-13 9.4.2 Pulse Accumulator Control Register.9-14 9.5 Computer Operating Properly Watchdog Function 9-15 9.6 Pulse Accumulator 9-15 9.6.1 Pulse Accumulator Control Register.9-17 9.6.2 Pulse Accumulator Count Register.9-17 9.6.3 Pulse Accumulator Status and Interrupt Bits 9-18 Appendix A ELECTRICAL CHARACTERISTICS Appendix B MECHANICAL DATA AND ORDERING INFORMATION B.1 Pin Assignments B-1 B.2 Package Dimensions.B-3 B.3 Ordering Information B-3 Appendix C DEVELOPMENT SUPPORT C.1 Development System Tools.C-1 C.2 MC68HC11D3 Development Tools C-1 INDEX MC68HC11D3 TA Figure Title Page LIST OF ILLUSTRATIONS 1-1 MC68HC11D3 Block Diagram 1-2 2-1 Pin Assignments for 44-Pin PLCC 2-1 2-2 Pin Assignments for 40-Pin DIP 2-2 2-3 External Reset Circuit 2-3 2-4 Common Crystal Connections 2-3 2-5 External Oscillator Connections 2-4 2-6 One Crystal Driving Two MCUs 2-4 3-1 Programming Model 3-1 3-2 Stacking Operations 3-3 4-1 Address/Data Demultiplexing 4-2 4-2 MC68HC11D3 Memory Map 4-3 4-3 RAM Standby MODB/VSTBY Connections 4-6 5-1 Processing Flow out of Reset (1 of 2)5-12 5-2 Interrupt Priority Resolution (1 of 2)5-14 5-3 Interrupt Source Resolution within SCI 5-16 7-1 SCI Transmitter Block Diagram 7-2 7-2 SCI Receiver Block Diagram 7-3 7-3 SCI Baud Rate Diagram 7-10 7-4 Interrupt Source Resolution within SCI 7-12 8-1 SPI Block Diagram 8-2 8-2 SPI Transfer Format 8-3 9-1 Timer Clock Divider Chains 9-2 9-2 Capture/Compare Block Diagram 9-4 9-3 Pulse Accumulator 9-16 A-1 Test Methods A-3 A-2 Timer Inputs A-4 A-3 POR and External Reset Timing Diagram A-5 A-4 STOP Recovery Timing Diagram A-6 A-5 WAIT Recovery Timing Diagram A-7 A-6 Port Write Timing Diagram A-8 A-7 Port Read Timing Diagram A-8 A-8 Multiplexed Expansion Bus Timing Diagram A-10 A-9 SPI Master Timing (CPHA = 0)A-12 TECHNI (Continued) Figure Title Page LIST OF ILLUSTRATIONS A-10 SPI Master Timing (CPHA = 1)A-12 A-11 SPI Slave Timing (CPHA = 0)A-13 A-12 SPI Slave Timing (CPHA = 1)A-13 B-1 40-Pin DIP B-1 B-2 44-Pin PLCC B-2 B-3 44-Pin QFP B-3 MC68HC11D3 TA Table Title Page LIST OF TABLES 2-1 Port Signal Functions.2-6 3-2 Instruction Set.3-8 4-1 Register and Control Bit Assignments 4-4 4-2 Hardware Mode Select Summary.4-6 4-3 RAM Mapping.4-9 4-4 Register Mapping.4-9 5-1 COP Time-out.5-2 5-2 Reset Cause, Reset Vector, and Operating Mode 5-4 5-3 Highest Priority Interrupt Selection 5-8 5-4 Interrupt and Reset Vector Assignments.5-9 5-5 Stacking Order on Entry to Interrupts 5-10 7-1 Baud Rate Prescale Selects.7-8 7-2 Baud Rate Selects.7-9 9-1 Timer Summary 9-3 9-2 Timer Control Configuration.9-5 9-3 Pulse Accumulator Timing.9-16 A-1 Maximum Ratings.A-1 A-2 Thermal Cha........