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1 ?F capacitors are recommended. See the Applicaiton Information section. A1, D8, D9, AVDD 3.3V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks. E8, E9, K1 K2 AVDD_5V 5.0V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks. J6, J7, K8, L3, AVDD_ADC 1.8V Analog power supply for ADC. M1, M2 C1, D1~D7, E3~E7, F3~F7, G1~G7, AVSS Analog ground. H3~H7,J3~J5, K6 Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or L2 CLKM_ADC through a 0.1?F capacitor. Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal L1 CLKP_ADC directly or through a 0.1?F capacitor. Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the 4X and 8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode, F9 CLKM_16X this pin becomes the quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X F8 CLKP_16X CLKP input. In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKP for the CW mixer. Can be floated if CW mode is not used. Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer G9 CLKM_1X to Figure

88 for details). In the 1X clock mode, this pin is the In-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the In-phase 1X CLKP for G8 CLKP_1X the CW mixer. Can be floated if CW mode is not used. Bias voltage and bypass to ground. ≥ 1?F is recommended. To suppress the ultra low frequency noise, B1 CM_BYP

10 ?F can be used. Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be E2 CW_IP_AMPINM connected between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be floated if not used.

4 Submit Documentation Feedback Copyright ? 2010C2012, Texas Instruments Incorporated Product Folder Link(s): AFE5808 AFE5808 www.ti.com SLOS688C CSEPTEMBER 2010CREVISED APRIL

2012 PIN FUNCTIONS (continued) PIN DESCRIPTION NO. NAME Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be E1 CW_IP_AMPINP connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be F1 CW_IP_OUTM connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used. Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be F2 CW_IP_OUTP connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used. Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to CW_QP_AMPIN J2 be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative M output when PGA test mode is enabled. Can be floated if not used. Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be J1 CW_QP_AMPINP connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to H1 CW_QP_OUTM be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used. Positive differential output........