PDF《PurePath Digital AMPLIFIER》

2003 C REVISED MAY

2003 www.ti.com

3 FUNCTIONAL BLOCK DIAGRAM Bootstrap Gate Drive DIFF RCVR LDR Bootstrap Gate Drive DIFF RCVR LDR Control/Sense Circuit Band-Gap Reference 1/2 H-Bridge 1/2 H-Bridge OUTPUTA OUTPUTA PVSS BOOTSTRAPB PVDDB1 PVDDB1 OUTPUTB OUTPUTB DVDD DVSS PVSS PWM_AP PWM_AM PWDN RESET SHUTDOWN ERR1 ERR0 LDROUTB VRFILT PVDDB2 PWM_BM PWM_BP PVDDA2 LDROUTA BOOTSTRAPA PVDDA1 PVDDA1 BIAS_A BIAS_B TAS5110A SLES079A C APRIL

2003 C REVISED MAY

2003 www.ti.com

4 SUGGESTED SYSTEM BLOCK DIAGRAMS ? USB ? IEEE

1394 ? S/PDIF ? ADC ? Automotive MOST Network Digital Audio TAS30xx I2C Audio Control TAS50xx TAS5110A Left Right ? Digital Parametric EQ ? Volume ? DRC ? Bass ? Treble ? Serial Audio Input Port ? Internal PLL ? Two H-Bridges TAS5110A L-C Filter L-C Filter Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor TI DSP ? Dolby AC-3 ? DTS ? Volume ? EQ ? DRC ? Bass ? Treble Home Theater DVD 6-Channel EncodedDigital Audio Source TAS50xx TAS5110A CH1 CH2 TAS50xx CH3 CH4 TAS50xx CH5 CH6

6 TAS5110A TAS5110A TAS5110A TAS5110A TAS5110A Left Right Surround Left Surround Right Center Subwoofer L-C Filter L-C Filter L-C Filter L-C Filter L-C Filter L-C Filter Figure 2. System #2: 6-Channel Audio Playback TAS5110A SLES079A C APRIL

2003 C REVISED MAY

2003 www.ti.com

5 Terminal Functions TERMINAL NAME DAD NO. I/O DESCRIPTION BIAS_A

6 I Connect external resistor to DVSS. BIAS_B

5 I Connect external resistor to DVSS. BOOTSTRAPA

19 O Bootstrap capacitor pin for H-bridge A BOOTSTRAPB

30 O Bootstrap capacitor pin for H-bridge B DVDD

11 ― 3.3-V digital voltage supply for logic DVSS 8, 9,

10 ― Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not connected externally to PVSS. See Figure 5. ERR1

14 O Error/warningreportindicator. This output is open drain with internal pullup resistor. ERR0

13 O Error/warningreportindicator. This output is open drain with internal pullup resistor. LDROUTA

18 O Low-voltage drop-out regulator output A (not to be used to supply current to external circuitry) LDROUTB

31 O Low-voltage drop-out regulator output B (not to be used to supply current to external circuitry) OUTPUTA 22,

23 O H-bridge output A OUTPUTB 26,

27 O H-bridge output B PVDDA1 20,

21 ― High-voltage power supply, H-bridge A PVDDA2

17 ― High-voltage power supply for low-dropout voltage regulator A-side PVDDB1 28,

29 ― High-voltage power supply, H-bridge B PVDDB2

32 ― High-voltage power supply for low-dropout voltage regulator B-side PVSS 24,

25 ― High-voltage power supply ground PWDN

4 I Power down = 0, normal mode =

1 PWM_AM

15 I PWM input A(C) PWM_AP

16 I PWM input A(+) PWM_BP

1 I PWM input B(+) PWM_BM

2 I PWM input B(C) RESET

3 I Reset and mute mode = 0, normal mode = 1;

when in reset mode, H-bridge MOSFETs are in low-low output state. Asserting the RESET signal low causes all fault conditions to be cleared. SHUTDOWN

12 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0;

when device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. VRFILT

7 O A filter capacitor must be added between the VRFILT and DVSS pins. NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted. Dualpins: OUTPUTA,OUTPUTB,PVDDA1,andPVDDB1musthavebothpinsconnectedexternallytothesamepointonthecircuitboard, respectively.BothPVSSpinsmustalsobeconnectedtogetherexternally.Thesemultiplepinsareforthehigh-currentDMOSoutputdevices. Failuretoconnectallthemultiplepinstothe same respective node results in excessive current flow in the internal bond wires and can cause thedevicetofail.Allelectricalcharacteristicsarespecifiedandmeasuredwithallofthemultiplepinsofeachtypeconnectedtoasinglenode. TAS5110A SLES079A C APRIL