PDF《PurePath Digital AMPLIFIER》

2003 C REVISED MAY

2003 www.ti.com

6 FUNCTIONAL DESCRIPTION PWM H-Bridge State Control The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side half-bridge and the B-side half-bridge. Bootstrapped Gate Drive The TAS5110A includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output. For example, a capacitor is connected between the BOOTSTRAPA pin and the OUTPUTA pin and another capacitor is connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally suppliedto the system, while providing a low-noise supply level for driving the high-side N-channel DMOS transistors. Low-Dropout Voltage Regulator Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return. For example, a capacitor is connected between the LDROUTA pin and the PVSS pin and another capacitor is connected between the LDROUTB pin and the PVSS pin. High-Current H-bridge Output Stage The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section immediately following. When the TAS5110A is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5110A is immediately shut down if any of the following error conditions occur: overcurrent, overtemperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low. H-Bridge Output Mapping The A-side half-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTION RESET PWDN PWM_AP PWM_AM SHUTDOWN OUTPUTA DESCRIPTION X X X X

0 0 or Hi-Z(1) Shutdown X

0 X X

1 Hi-Z Power down

0 1 X X

1 0 Reset

1 1

0 0

0 0 Shutdown

1 1

0 1

1 0 Normal

1 1

1 0

1 1 Normal

1 1

1 1

0 0 Shutdown (1) Output is

0 for low voltage, overtemperature, and illegal input. Hi-Z is for overcurrent. The B-side half-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTION RESET PWDN PWM_BP PWM_BM SHUTDOWN OUTPUTB DESCRIPTION X X X X

0 0 or Hi-Z(1) Shutdown X

0 X X

1 Hi-Z Power down

0 1 X X

1 0 Reset

1 1

0 0

0 0 Shutdown

1 1

0 1

1 0 Normal

1 1

1 0

1 1 Normal

1 1

1 1

0 0 Shutdown (1) Output is

0 for low voltage, overtemperature, or illegal input. Hi-Z is for overcurrent. TAS5110A SLES079A C APRIL

2003 C REVISED MAY

2003 www.ti.com

7 Control/Sense Circuitry The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and SHUTDOWN. The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the low-low state and resets the overcurrent shutdown latch. The PWDN pin overrides the RESET pin. The ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5110A as shown in the following table. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections can be made by the user with other external control devices. The short-circuit protect error condition latches the TAS5110A in this shutdown state and forces the H-bridge outputs to the Hi-Z state until the device is reset by means of the RESET pin. The illegal PWM input state, overtemperature, and low regulator voltage error conditions does not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the low-low state and the TAS5110A returns to normal operation as soon as the error condition ends.........